Record Low Contact Resistance Research Articles

High-Performance Short-Channel Top-Gate Indium-Tin-Oxide Transistors by Optimized Gate Dielectric

In this work, high-performance top-gate indium-tin-oxide (ITO) transistors with high carrier mobility of 60 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V∙s have been successfully demonstrated using optimized atomic layer deposited (ALD) La-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as the top-gate dielectric. The scaled device with a channel length of 50 nm exhibits a high current on/off ratio over 7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> owing to the excellent electrostatic control. A maximum output current of 1680 μA/μm with a remarkable carrier velocity of 0.87×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cm/s has also been achieved due to the record low contact resistance of 180 Ω∙μm. The on- and off-state performance of our ITO transistors are the highest among previous top-gate amorphous oxide semiconductors.

Vacancy Assisted Bilayer Graphene Contact for Monolayer Graphene Channel Devices

Contact engineering of monolayer graphene channel FETs has been a fundamental limiting factor hindering its intrinsic benefits for applications such as THz electronics, quantum sensing, quantum computing/communication devices, etc. This experimental work presents a unique technique to achieve record low contact resistance using carbon vacancy-assisted bilayer graphene contact. The bilayer graphene contact with engineered carbon vacancies lowered the metal-graphene interfacial distance and enhanced the atomic orbital overlap, eventually lowering the contact resistance. The interfacial properties and orbital interactions are investigated using density functional theory and non equilibrium Green’s function based transport computations. The reduction in contact resistance is then experimentally validated using unique Kelvin probe structures with monolayer and bilayer contacts. The captured contact resistance is as low as ~36 Ω.μm, which is a record low contact resistance value reported to date.

Excited state spectroscopy and spin splitting in single layer MoS2 quantum dots.

Semiconducting transition metal dichalcogenides (TMDCs) are very promising materials for quantum dots and spin-qubit implementation. Reliable operation of spin qubits requires the knowledge of the Landé g-factor, which can be measured by exploiting the discrete energy spectrum on a quantum dot. However, the quantum dots realized in TMDCs are yet to reach the required control and quality for reliable measurement of excited state spectroscopy and the g-factor, particularly in atomically thin layers. Quantum dot sizes reported in TMDCs so far are not small enough to observe discrete energy levels on them. Here, we report on electron transport through discrete energy levels of quantum dots in a single layer MoS2 isolated from its environment using a dual gate geometry. The quantum dot energy levels are separated by a few (5-6) meV such that the ground state and the first excited state transitions are clearly visible, thanks to the low contact resistance of ∼700 Ω and relatively low gate voltages. This well-resolved energy separation allowed us to accurately measure the ground state g-factor of ∼5 in MoS2 quantum dots. We observed a spin-filling sequence in our quantum dots under a perpendicular magnetic field. Such a system offers an excellent testbed to measure the key parameters for evaluation and implementation of spin-valley qubits in TMDCs, thus accelerating the development of quantum systems in two-dimensional semiconducting TMDCs.

Low Resistance Ohmic Contact on Epitaxial MOVPE Grown β-Ga2O3 and β-(AlxGa1−x)2O3 Films

We report on the realization of record low resistance Ohmic contacts to MOVPE-grown heavily Si-doped $\beta$-Ga$_2$O$_3$ and $\beta$-(Al$_x$Ga$_1-x$)$_2$ O$_3$ epitaxial films. Transfer length measurement (TLM) patterns were fabricated on the heavily Si-doped homoepitaxial $\beta$-Ga$_2$O$_3$ films with electron concentration (n) ranging from 1.77 to 3.23e20 cm^-3. Record low specific contact resistance and total contact resistance (Rc) of 1.62e-7 Ohm.cm^2 and 0.023 Ohm.mm were realized for $\beta$-Ga$_2$O$_3$: Si films with n > 3e20 cm^-3. TLM structures were also fabricated on heavily Si doped coherently strained $\beta$-(Al$_x$Ga$_1-x$)$_2$ O$_3$ (x=12%, 17% and 22%) films. The film with 12% Al composition (n=1.23e20 cm^-3) showed \r{ho}c of 5.85e-6 Ohm.cm^2, but it increased to 2.19e-4 Ohm.cm^2 for a layer with a 22% Al composition. Annealing the samples post metal deposition has generally led to a decrease in contact resistance, but for high Al content $\beta$-(Al$_x$Ga$_1-x$)$_2$ O$_3$, the contact resistance did not change significantly after the annealing process. The low contact resistance values measured in this work are very promising for the fabrication of high frequency power devices.

AlN/Al0.5Ga0.5N HEMTs with heavily Si-doped degenerate GaN contacts prepared via pulsed sputtering

This paper reports AlN barrier Al0.5Ga0.5N high electron mobility transistors (HEMTs) with heavily Si-doped degenerate GaN contacts prepared by pulsed sputtering deposition. Selectively regrown n-type GaN contacts exhibit typical degenerate properties with the electron concentration and mobility of 2.6 × 1020 cm−3 and 115 cm2 V−1 s−1, respectively, resulting in a record low contact resistance R C of 0.43 Ω mm for the AlN/Al0.5Ga0.5N HEMTs. The AlN/Al0.5Ga0.5N HEMTs displayed a remarkable DC output characteristic with a maximum drain current density of 250 mA mm−1, a transconductance of 32 mS mm−1, and an On/Off ratio >106. The present results show potential overcoming challenges in ohmic contact formation for high-power and high-frequency AlGaN electron devices with high Al composition.

Alcohol-Based Sulfur Treatment for Improved Performance and Yield in Local Back-Gated and Channel-Length-Scaled MoS₂ FETs

Achieving good ohmic contacts, with minimum variability, has remained a challenge for field-effect transistors (FETs) using molybdenum disulfide (MoS2). Surface state engineering using ammonium sulfide is a great way to obtain superior and reliable contacts on MoS2 using high-work-function metals such as nickel. However, the process is aggressive to thin gate dielectrics hampering device yield. We report on an improved sulfur treatment process in an alcoholic medium that is less aggressive to thin gate dielectrics and offers a record low Schottky barrier height of 131 meV on Ni–MoS2 contacts. We demonstrate the suitability of this process with channel length scaling ( ${L}_{\text {G}}$ from 500 to 80 nm) on global back-gated FETs with a record low contact resistance of $1.3~\text {k}\Omega \cdot \mu \text {m}$ for 80-nm FET. We also demonstrate the compatibility of the proposed process with local back-gated FETs on thin high- ${k}$ HfO2 gate dielectrics, which is crucial for scalable process integration in realizing integrated circuits on 2-D materials.

Self-Terminated Surface Monolayer Oxidation Induced Robust Degenerate Doping in MoTe2 for Low Contact Resistance.

We introduce an effective method to degenerately dope MoTe2 by oxidizing its surface into the p-dopant MoOx in oxygen plasma. As a self-terminated process, the oxidation is restricted only in the very top layer, therefore offering us an easy and efficient control. The degenerate p-doping with the hole concentration of 2.5 × 1013 cm-2 can be obtained by applying a ∼300 s O2 plasma treatment. Using the degenerately doped MoTe2, we demonstrate a record low contact resistance of 0.6 kΩ μm for MoTe2. Our measurement highlights an excellent stability for the plasma-doped MoTe2. The doped characteristics are robust with no significant degradation even after a one-year exposure to the air. The oxygen plasma doping technique is compatible with the conventional semiconductor processes, which can be utilized to realize high-performance MoTe2 field-effect transistors (FETs) or tunnel FETs in the future.

Ultrafast 27\u2009GHz cutoff frequency in vertical WSe2 Schottky diodes with extremely low contact resistance

Ultra-thin two-dimensional semiconducting crystals in their monolayer and few-layer forms show promising aspects in nanoelectronic applications. However, the ultra-thin nature of two-dimensional crystals inevitably results in high contact resistance from limited channel/contact volume as well as device-to-device variability, which seriously limit reliable applications using two-dimensional semiconductors. Here, we incorporate rather thick two-dimensional layered semiconducting crystals for reliable vertical diodes showing excellent Ohmic and Schottky contacts. Using the vertical transport of WSe2, we demonstrate devices which are functional at various frequency ranges from megahertz AM demodulation of audio signals, to gigahertz rectification for fifth-generation wireless electronics, to ultraviolet–visible photodetection. The WSe2 exhibits an excellent Ohmic contact to bottom platinum electrode with record-low contact resistance (~50 Ω) and an exemplary Schottky junction to top transparent conducting oxide electrode. Our semitransparent vertical WSe2 Schottky diodes could be a key component of future high frequency electronics in the era of fifth-generation wireless communication.

Formation of Low-Resistivity Au/Mo/Ti Ohmic Contacts to p-Diamond Epitaxial Layers

The formation of Au/Mo/Ti ohmic contacts to p-diamond epitaxial films has been studied. Specifically, the influence of annealing on the electrical properties and structure of contacts has been investigated. It has been shown that the upper gold layer protects the contact system against oxidation up to 850°C during RTA unlike the case of a “simplified” Au-free Mo/Ti system frequently used in today’s solutions. In Mo-free Au/Ti systems, high-temperature annealing causes effective diffusion of titanium into the gold layer, which deteriorates the protective properties of the latter and enhances oxygen diffusion toward the interface with diamond. Oxidation of the Ti/C contact area prevents the formation of a titanium carbide conducting layer, which has high adhesion to diamond. The role of various factors, namely, annealing to form titanium carbide, heavy doping of diamond with boron, and crystal perfection of diamond films, in lowering the contact resistance, has been estimated. For doped epitaxial films grown on single-sector substrates, unalloyed ohmic contacts with a record low contact resistance of 4 × 10–7 Ω/cm2 have been obtained.

(Invited) Vertically Stacked n Channel and p Channel Transistors

The Si FinFET architecture has been used in mass production in the industry for several technology nodes. Recently, the horizontal stacked channel GAAFET becomes a good candidate to achieve better power-performance properties than FinFETs in a certain area due to the promise of well controlled epitaxy, selective etching, and GAA nature. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate the CVD grown, vertically-stacked strained GeSi channels for nGAAFETs and GeSn channels for pGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to improve the electrostatics for Ge-based channel GAAFETs while the stacked GeSn pGAAFETs has record high ION and Gm with highly competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. In addition, record low contact resistivity (4.4x10-10 ohm-cm2) to Ge using in-situ B and Sn incorporation by CVD is also demonstrated with low thermal budget (≦400oC) and without any Ga doping. The Ge/Ge0.85Si0.15 and Ge/Ge0.91Sn0.09 multi layers are epitaxially grown on SOI substrates by CVD. Ge buffer layers and sacrificial layers are not only used to be selectively etched in preference to GeSi and GeSn to form the vertical stacked GeSi channels and GeSn channels, but also to stress both GeSi N-channels tensily and GeSn P-channels compressively, respectively. The high temperature anneal for the buffer can confine the dislocations at the bottom of Ge buffer and reduce the defect density in the channels to improve the device performance. The heavy in-situ doping of source and drain, post metal annealing, laser annealing for nFETs, and NiGe/ PtGeSn formation can reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi and GeSn channels. For GeSi nFETs, rhe △Ec between GeSi and Si is nearly zero. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. The Vt difference between GeSi and Si can be tuned by the channel size optimizing. By narrowing the GeSi channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive Vt for GeSi than Si is observed. The Si channel turn on first with good SS=76mV/dec and DIBL=36mV/V due to low Dit and good short channel control. Ioff is also dramatically reduced and the Ion/Ioff are improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow GeSi channels. The improved flicker noise also indicates the enhanced reliability. For GeSn pFETs, the {111} plane has high mobility, low dangling bond density, low Dit, and better gate control than the rectangular channel. Vertically stacked triangular Ge0.91Sn0.09 pGAAFETs with compressive strain of ~2% in the channel and low surface roughness are achieved by orientation dependent etching on natural etching stop {111} plane by the optimized etching process. The 22% reduction of SSlin=84mV/dec, 50% improvement of ION=120mA/mm at VOV=VDS=-0.5V, and 71% improvement of Gm=312mS/mm at VDS=-0.5V are achieved as compared to our previous work of 3 stacked Ge0.93Sn0.07 nanosheets. The device has the record ION of 19.3mA per stack at VOV= VDS=-0.5V and record Gm,max of 50.2mS per stack at VDS=-0.5V with competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. For the p-type contact resistivity (ρc) reduction, B (>1x1021cm-3) and Sn (>12%) segregations at the Ti/GeSn:B interface are used to reduce the hole tunneling distance and the Schottky barrier height of holes, respectively. The GeSn:B is grown by CVD using Ge2H6, SnCl4, and B2H6 in H2 ambient at ≦320oC. Due to the Sn segregation, there is no need to grow high-[Sn] GeSn layer for the ρc reduction, which makes the pseudomorphic growth of the compressively strained GeSn possible. After metal deposition at elevated temperature and 400oC annealing, the ρc of 4.4x10-10 ohm-cm2 is achieved. Ge nGAAFETs, GeSn pGAAFETs, and the S/D with extremely low contact resistivity fabricated by CVD growth and optimized process are compatible with Si technologies and becomes promising candidates for CMOS applications in the future technology nodes. Acknowledgements: The MOST (107-2218-E-002-044-, 107-2622-8-002-018) and MOE (NTU-CC-108L891701), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.

Small contact resistance and high-frequency operation of flexible low-voltage inverted coplanar organic transistors

The contact resistance in organic thin-film transistors (TFTs) is the limiting factor in the development of high-frequency organic TFTs. In devices fabricated in the inverted (bottom-gate) device architecture, staggered (top-contact) organic TFTs have usually shown or are predicted to show lower contact resistance than coplanar (bottom-contact) organic TFTs. However, through comparison of organic TFTs with different gate-dielectric thicknesses based on the small-molecule organic semiconductor 2,9-diphenyl-dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene, we show the potential for bottom-contact TFTs to have lower contact resistance than top-contact TFTs, provided the gate dielectric is sufficiently thin and an interface layer such as pentafluorobenzenethiol is used to treat the surface of the source and drain contacts. We demonstrate bottom-contact TFTs fabricated on flexible plastic substrates with record-low contact resistance (29 Ωcm), record subthreshold swing (62 mV/decade), and signal-propagation delays in 11-stage unipolar ring oscillators as short as 138 ns per stage, all at operating voltages of about 3 V.

Record-low contact resistance for InAlN/AlN/GaN high electron mobility transistors on Si with non-gold metal

We have demonstrated 0.17-µm gate-length In0.17Al0.83N/GaN high-electron-mobility transistors (HEMTs) on Si(111) substrates using a non-gold metal stack (Ta/Si/Ti/Al/Ni/Ta) with a record-low ohmic contact resistance (Rc) of 0.36 Ω mm. This contact resistance is comparable to the conventional gold-based (Ti/Al/Ni/Au) ohmic contact resistance (Rc = 0.33 Ω mm). A non-gold ohmic contact exhibited a smooth surface morphology with a root mean square surface roughness of ∼2.1 nm (scan area of 5 × 5 µm2). The HEMTs exhibited a maximum drain current density of 1110 mA/mm, a maximum extrinsic transconductance of 353 mS/mm, a unity current gain cutoff frequency of 48 GHz, and a maximum oscillation frequency of 66 GHz. These devices exhibited a very small (<8%) drain current collapse for the quiescent biases (Vgs0 = −5 V, Vds0 = 10 V) with a pulse width/period of 200 ns/1 ms. These results demonstrate the feasibility of using a non-gold metal stack as a low Rc ohmic contact for the realization of high-frequency operating InAlN/AlN/GaN HEMTs on Si substrates without using recess etching and regrowth processes.

AlGaN/GaN HEMTs on Si by MBE with regrown contacts and fT = 153 GHz

AbstractAlGaN/GaN high‐electron‐mobility transistors (HEMT) have been grown by radio frequency molecular beam epi‐taxy (RF‐MBE) on 3″ Si substrates. A record low contact resistance Rc ˜ 0.11 Ω.mm has been achieved for GaN HEMTs on Si by using non alloyed ohmic contacts regrown by MBE. Owing to the low contact resistance a 75‐nm gate length unpassivated HEMT shows intrinsic current gain cut‐off frequency fT =153 GHz, a high saturation drain current density&gt; 1.3 A/mm and a low RON of 1 Ω.mm, among the best reported for HEMTs on Si. With further scaling GaN HEMTs on Si can compete in the high‐performance RF arena with similar devices on SiC, while exploiting the many advantages of integration with Si. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)