Reconfigurable Processing Elements Research Articles

Implementation Of Reconfigurable Processing Elements For Image Processing Application

Reconfigurable embedded processors are a special class of processors comprising an extended instruction set that is implemented using a reconfigurable fabric. The instruction -set extension is typically appl ication speci fic, but i t is not required to finalize i t when designing the processor. The reconfigurable fabric consist of processing elements (PE) allows that the accelerators that are used to implement the instruction -set may be reconfigured during design time wi thout affecting the functionali ty of the working processor. This paper presents the technique to reconfigure using PE for digi tal image processing (DIP) application. We have tried to implement i t for image segmentation . Keywords-Reconfigurable Processor (RP), Reconfigurable Processing element (PE), Image segmentation, FPGA.

A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA

A secure reconfigurable cryptographic co-processor supporting multiple algorithms of advanced encryption standard (AES), data encryption standard (DES), rivest cipher 6, and international data encryption algorithm is proposed using its own reconfigurable feature to resist side-channel attack (SCA). It is integrated into a system-on-chip and fabricated in $0.18~\boldsymbol {\mu }\text{m}$ CMOS process with 1.8 V supply voltage and 100 MHz max frequency. Several kinds of specific countermeasures are proposed to hide leakage information by utilizing idle reconfigurable processing elements to do dummy operations. Its advantages lie in its little impact on area and frequency as well as high flexibility after silicon that countermeasures can also be reconfigured. Furthermore, different protections including several kinds of global countermeasures and encryption flow related countermeasures can be stacked, thus the security level can be tuned by trading for some performance or power consumption. Experimental SCA attack results show that it resists simple power analysis and differential power analysis without revealing the subkey. For correlation-based electromagnetic analysis (EMA) of DES configuration, it increases $36\boldsymbol {\times } $ measure to disclosure when applied with partial countermeasures compared to unprotected DES. As to AES configuration with full countermeasures, it resists EMA with no sign to reveal the right subkey for up to 1.2 million electromagnetic traces.

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Field-programmable gate arrays (FPGAs) can be considered to be the most popular and successful platform for evolvable hardware. They allow one to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Virtual reconfiguration is based on the change of functionality by hardware components implemented on top of FPGA resources. Native reconfiguration changes the FPGA resources directly by means provided by the FPGA manufacturer. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all-programmable system-on-chip. The proposed architecture offers high flexibility in comparison with other evolvable hardware systems by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast evaluation of candidate solutions. The proposed architecture is evaluated by evolutionary design of switching image filters and edge detectors. The experimental results demonstrate advantages over the previous approaches considering the time required for evolution, area overhead, and flexibility.

Application-specific coarse-grained reconfigurable array: architecture and design methodology

Coarse-grained reconfigurable arrays (CGRAs) have shown potential for application in embedded systems in recent years. Numerous reconfigurable processing elements (PEs) in CGRAs provide flexibility while maintaining high performance by exploring different levels of parallelism. However, a difference remains between the CGRA and the application-specific integrated circuit (ASIC). Some application domains, such as software-defined radios (SDRs), require flexibility with performance demand increases. More effective CGRA architectures are expected to be developed. Customisation of a CGRA according to its application can improve performance and efficiency. This study proposes an application-specific CGRA architecture template composed of generic PEs (GPEs) and special PEs (SPEs). The hardware of the SPE can be customised to accelerate specific computational patterns. An automatic design methodology that includes pattern identification and application-specific function unit generation is also presented. A mapping algorithm based on ant colony optimisation is provided. Experimental results on the SDR target domain show that compared with other ordinary and application-specific reconfigurable architectures, the CGRA generated by the proposed method performs more efficiently for given applications.

Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation

Integer pixel motion estimation (IME) is one crucial module with high complexity in high-definition video encoder. Efficient algorithm and architecture joint design is supposed to tradeoff multiple target parameters including throughput capacity, logic gate, on-chip SRAM size, memory bandwidth, and rate distortion performance. Data organization and on-chip buffer structure are crucial factors for IME architecture design, accounting for multiple target performance tradeoff. In this work, we combine global hierarchical search and local full search to propose hardware efficient IME algorithm, and then propose hardware VLSI architecture with optimized on-chip buffer structure. The major contribution of this work is characterized by: (1) improved hierarchical IME algorithm with presearch and deliberate data organization, (2) multistage on-chip reference pixel buffer structure with high data reuse between integer and fraction pixel motion estimations, (3) highly reused and reconfigurable processing element structure. The optimized data organization and buffer structure achieves nearly 70 % buffer saving with less than average 0.08, 0.12 dB the worst case, PSNR degradation compared with full search based architecture. At the hardware cost of 336 and 382 K logic gate and 20 kB SRAM, the proposed architecture achieves the throughput of 384 and 272 cycles per macroblock, at system frequency of 95 and 264 MHz for 1080p and QFHD @30fps format video coding.

Investigation of vertical cavity surface emitting laser dynamics for neuromorphic photonic systems

We report an approach based upon vertical cavity surface emitting lasers (VCSELs) to reproduce optically different behaviors exhibited by biological neurons but on a much faster timescale. The technique proposed is based on the polarization switching and nonlinear dynamics induced in a single VCSEL under polarized optical injection. The particular attributes of VCSELs and the simple experimental configuration used in this work offer prospects of fast, reconfigurable processing elements with excellent fan-out and scaling potentials for use in future computational paradigms and artificial neural networks.

Methodology for Implementing Scalable Run-Time Reconfigurable Devices

Methodology for Implementing Scalable Run-Time Reconfigurable Devices The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.

Collaboration of reconfigurable processors in grid computing: Theory and application

Traditional grid networks employ General Purpose Processors (GPPs) as their main processing elements. Incorporating reconfigurable processing elements in such networks can be a promising technology to increase their performance. In this paper, we propose and simulate collaboration of reconfigurable processors in grid computing. Collaborative Reconfigurable Grid Computing (CRGC) employs the availability of any reconfigurable processor to accelerate compute-intensive applications such as multimedia kernels. We explore the mapping of some compute-intensive multimedia kernels such as the 2D DWT and the co-occurrence matrix in the CRGC. These multimedia kernels are simulated as an independent set of gridlets submitted to a software simulator called CRGridSim. In addition, we analyze the lower and upper bounds of performance for CRGC. Our experimental results show that the CRGC approach improves performance up to 7.2 × and 2.5 × compared to a single GPP and the collaboration of GPPs, respectively, when assuming a speedup of 10 of the reconfigurable processors in a grid with 4 nodes.

Multi-functional systolic array with reconfigurable micro-power processing elements

This paper presents the design and implementation of high performance bi-directional linear systolic array (BLSA) with low-power, reconfigurable processing elements (PE). The BLSA acts as a hardware accelerator for implementing a broad class of problems which are met in a variety of applications such as digital signal processing, computer graphics, graph algorithms, etc. We define a unique algorithm representation for solving problems such as matrix multiplication, transitive closure, finding critical path in a graph, finding all-pairs shortest paths in a graph, etc. The algorithm is mapped into a BLSA with reconfigurable PEs. A clock gating technique is used to minimize power-consumption of a multi-functional PE. Performance of the BLSA are considered from the aspects of power-consumption and communication bandwidth. Using clock gating technique we achieve PE power reduction of 85% in average. Communication bandwidth is considered for different number of PEs in the BLSA and different operand size. The obtained results are in the range of 442 up to 9460 MB/s, i.e. bandwidth of our design is better for larger array and operand size. A lower-power, reconfigurable PE is realized using Xilinx FPGA chips.

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse‐grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase‐FIR filters, phase shifters, DFTs, and Polyphase‐DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time sharing computation of high‐throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector‐matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA‐based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high‐density computing.

A minimization version of a directed subgraph homeomorphism problem

We consider a special case of the directed subgraph homeomorphism or topological minor problem, where the host graph has a specific regular structure. Given an acyclic directed pattern graph, we are looking for a host graph of minimal height which still allows for an embedding. This problem has applications in compiler design for certain coarse-grain reconfigurable architectures. In this application domain, the task is to simultaneously schedule, bind and route a so-called data-flow graph, where vertices represent operations and arcs stand for data dependencies between the operations, given an orthogonal grid structure of reconfigurable processing elements (PEs) that have restricted communication abilities. We show that the problem of simultaneously scheduling, binding and routing is NP-complete by describing a logic engine reduction from NAE-3-SAT. This result holds even when the input graph is a directed tree with maximum indegree two. We also give a |V|3/2-approximation algorithm.

CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders

To design the hardware for image signal processing pipelines in digital still cameras (DSCs) and video camcoders, it is a dilemma for conventional solutions, such as application-specific integrated circuits (ASICs) and digital signal processors (DSPs), to achieve high processing capability at low cost while maintaining high flexibility for various algorithms. With the observation of the characteristics of image signal-processing pipelines, including the different requirements for different operation modes and the algorithmic similarity of image-processing tasks, a new coarse-grained reconfigurable image stream processor (CRISP) is proposed in this paper. The design idea is to devote low-cost hardware for the requirements in the preview mode and add some hardware resources for higher flexibility and processing capability in the picture-taking mode. With the coarse-grained reconfigurable stage processing elements designed for image signal-processing tasks and the reconfigurable interconnection unit with unified communication protocol, CRISP can be reconfigured as an efficient dedicated hardware in the preview mode, and it can act like a flexible DSP for the picture-taking mode with different contexts. Implementation result shows that the core (die) size is 5 mm2 (7.72 mm2) with TSMC 0.18-mum process, and the power consumption is 218 mW at 1.8 V. At the working frequency of 115 MHz, the processor is capable of processing 11 M-pixel still images at 10 fps for DSCs or 1920 times 1080 video frames at 55 fps for camcorders. CRISP can execute image pipelines 83 times faster than the state-of-the-art DSP with only about one-tenth die size.

Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

Multimedia applications, like, e.g., 3-D games and video decoders, are typically composed of communicating tasks. Their target embedded computing platforms (e.g., TI OMAP3, IBM Cell) contain multiple heterogeneous processing elements. At application design-time, it is often unknown which applications will execute simultaneously. Hence, resource assignment decisions need to be made by a run-time manager. Run-time assignment of these communicating tasks onto the communication and computation resources of such a multiprocessor platform is a challenging task. In the presence of fine-grain reconfigurable hardware processing elements, the run-time manager also needs to consider the creation of a so-called configuration hierarchy. Instead of executing a dedicated hardware task, the fine-grain reconfigurable hardware fabric hosts a programmable softcore block that, in turn, executes the task functionality. Hence, the next challenge for run-time management is to efficiently handle a configuration hierarchy. This paper details a run-time task assignment heuristic that performs fast and efficient task assignment in a multiprocessor system-on-chip containing fine-grain reconfigurable hardware tiles. In addition, this algorithm is capable of managing a configuration hierarchy. We show that being capable of handling a configuration hierarchy significantly improves the task assignment performance (i.e., success rate and assignment quality). In several cases, adding a configuration hierarchy improves the assignment success rate of the assignment heuristic by 20%.

SLOPES: Hardware–Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs

In this paper, we present a multiobjective hardware-software cosynthesis system, called SLOPES, for multirate low-power real-time distributed embedded systems consisting of dynamically reconfigurable field-programmable gate arrays (FPGAs), processors, and heterogeneous communication resources. This cosynthesis algorithm simultaneously optimizes system price and average power consumption. First, we present an evolutionary algorithm that automatically determines the quantities and types of system resources, assigns tasks to different potentially reconfigurable processing elements, and assigns communication events to communication resources. Second, we propose a dynamic priority multirate scheduling algorithm to determine the times at which all the tasks and communication events in the system occur. This two-dimensional scheduling algorithm determines task priorities based on real-time constraints and detailed frame-by-frame FPGA reconfiguration overhead information. Experimental results indicate that the proposed method reduces schedule length by an average of 34.3% and reconfiguration energy by an average of 40.4%, compared to a method that does not consider the effect of partial reconfiguration during synthesis. SLOPES yields multiple system architectures that tradeoff system price and average power consumption under real-time constraints

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 ?m 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.

Encodage linéaire d'automates pondérés. Filtrage de motifs génomiques et application sur l'architecture prototype R-disk

We show that the linear encoding scheme (or one-hot scheme) efficiently simulates weighted finite automata (WFA). Those automata carry weights on every transition and model substitution errors in proteic patterns. Automata with t transitions can be avantageously hardwired with 0(t) operators. This scheme solves pattern matching problems by feeding a pipeline with one character every clock cycle. Such automata are well suited for use in FPGA devices, especially within the R-disk prototype, a hardware architecture devoted to content-based searches inside non-indexed large databanks: data is filtered on-the-fly at the output of storage devices, using distributed and reconfigurable processing elements. This improves the speed of parsing genomic databanks.

High performance hardware accelerator for design-error simulation

Error simulation is used to validate designs by providing simulation results, as well as simulation coverage metrics, based on design-error modelling and detection. Hardware acceleration is a viable approach to achieve efficient error simulation for large systems. In this research, the first hardware accelerator for design-error simulation purposes has been developed. The hardware accelerator uses a reconfigurable mesh-type processing element array, with direct mapping strategy, which establishes a basis for good approximation to breadboarding. In addition, a new embedded parallel algorithm is introduced to perform high speed and cost-effective design-error simulation. Using a cost–performance ratio, the performance is compared to a software simulation. Results show that this first hardware accelerator for error simulation is much faster, in terms of computation time, than software simulation and more cost effective.

FPGAs as reconfigurable processing elements

In most applications, FPGAs are used to implement glue logic, providing the advantages of high integration levels without the expense and risk of custom ASIC development. However, as SRAM-based FPGA devices have increased in capability, their use as in-system-configurable computing elements is receiving considerable attention. Indeed, reconfigurable FPGA technology holds the potential for reshaping the future of computing by providing the capability to dynamically alter a computer's hardware resources to optimally service immediate computational needs. Computing circuits built from SRAM-based FPGAs can meet the true goal of parallel processing-executing algorithms in circuitry with the inherent parallelism of hardware, while avoiding the instruction fetch and load/store bottlenecks of traditional von Neumann architectures. There are many computationally-intensive algorithms that can benefit from being partially or wholly implemented in hardware. Typically, these algorithms are too specialized to justify the expense of manufacturing custom IC devices.

Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL

The authors present an integrated computer-aided design environment, the VAR (VHDL-based array reconfiguration) system, for the tasks of design, reconfiguration, simulation, and evaluation in an architecture modeled by VHDL. An easily diagnosable and reconfigurable two-dimensional defect-tolerant processing element (PE) switch lattice array is used as an example to illustrate the methodology of VAR. VAR allows the designers study and evaluate fault diagnosis and reconfiguration algorithms by inserting faults, which are generated based on manufacturing yield data, into the array and then locating the fault PEs as well as simulating the reconfiguration process. Thus, VAR can assist the designers in evaluating the different combinations of fault patterns, fault diagnosis algorithms, and reconfigurable architectures through a complete set of figures of merit which aim at architectural improvements. Extensive simulation and evaluation have been performed to demonstrate and support the effectiveness of VAR. >