Reconfigurable Network-on-Chip Research Articles

Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

PurposeThe small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput.Design/methodology/approachTo address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA.FindingsIn the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.Originality/valueIn the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

Design of a reconfigurable network-on-chip for next generation FPGAs using Dynamic Partial Reconfiguration

Introducing the reconfigurability concept into one of the most ramping and trending design platforms like the NoC is considered a good opportunity for gaining the most out of them. The high flexibility and full customization of the reconfigurable NoC could open the door for a completely adaptive NoC that suits a large number of benchmarks according to runtime needs and requirements.The main objective of this work is to present the Dynamic Partial Reconfiguration (DPR) support to CONNECT Network-on-Chip (NoC) for Field Programmable Gate Array (FPGA) applications. It also analyzes the effect of this reconfigurability on the performance of the network and how reconfigurability could lead to area and power saving. Reconfigurability during runtime leads to more flexible NoCs and enables full customization for dynamic reconfigurable applications. In comparison with static NoCs, dynamically reconfigurable NoCs achieve more area utilization by reusing a part of the network area resources when it is not required during runtime. A reconfiguration tool is developed helping the designer to decide the optimal network structure for every application used. The reconfiguration tool requires as inputs the minimum needed throughput and the expected traffic load. Those inputs are used to decide the best network configuration and the minimum area that achieves those requirements.

A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs

In-memory computing reduces latency and energy consumption of Deep Neural Networks (DNNs) by reducing the number of off-chip memory accesses. However, crossbar-based in-memory computing may significantly increase the volume of on-chip communication since the weights and activations are on-chip. State-of-the-art interconnect methodologies for in-memory computing deploy a bus-based network or mesh-based Network-on-Chip (NoC). Our experiments show that up to 90% of the total inference latency of a DNN hardware is spent on on-chip communication when the bus-based network is used. To reduce the communication latency, we propose a methodology to generate an NoC architecture along with a scheduling technique customized for different DNNs. We prove mathematically that the generated NoC architecture and corresponding schedules achieve the minimum possible communication latency for a given DNN. Furthermore, we generalize the proposed solution for edge computing and cloud computing. Experimental evaluations on a wide range of DNNs show that the proposed NoC architecture enables 20%–80% reduction in communication latency with respect to state-of-the-art interconnect solutions.

Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip

The communication latency in traditional network-on-chip (NoC) with hop-by-hop traversal is inherently restricted by the distance between source-destination communicating pairs. SMART, as one of the dynamically reconfigurable NoC architectures, enables the new feature of single-cycle long-distance communication by building a direct bypass path between distant cores dynamically at runtime. With the increasing of the number of integrated cores in multi/many-core systems, SMART has been deemed a promising communication backbone in such systems. However, SMART is generally optimized for average-case performance for best-effort traffics, not offering real-time guaranteed services for real-time traffics, and thus SMART often shows extremely poor real-time performance (e.g., schedulability). To make SMART latency-predictable for real-time traffics, by combining with the single-cycle bypass forwarding technique, in this article, we first propose a priority-preemptive scheduling to allow contending packets to be arbitrated according to predefined priorities. Based on the priority-based scheduling, for the real-time packet flows with given flow mapping and predefined priorities, we then propose a real-time communication analysis model, by considering shared virtual channels (or priority levels) and arbitrary-deadline real-time packet flows, to predict the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">worst-case communication latency</i> and validate the schedulability. Through theoretical and experimental comparison, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">worst-case communication latency</i> of the analyzed packet flows is reduced significantly compared with that of the traditional priority-preemptive NoCs with hop-by-hop traversal and the original distance-based SMART, thus improving the schedulability.

Reconfigurable on-chip interconnection networks for high performance embedded SoC design

Abstract System on Chip (SoC) based embedded devices are providing key solutions to meet the demands of current and future high-performance embedded applications. These solutions become critical when the SoC IC designs are affected by the limitation of sub nanometer technologies that cannot be shrunk further. Network on Chip (NoC) is a scalable communication system that can provide efficient solutions for on-chip interconnection problems of SoCs such as re-configurability for multiple embedded applications. Most of the reconfigurable NoCs presented in the past improve performance of SoC at the expense of higher power and additional hardware. In this paper, we present a novel high-performance re-configurable NoC architecture that can improve the performance along with similar or improved power requirements of the system for different SoC applications. The proposed NoC architecture can also be considered as a hard IP for future partially configurable FPGA devices. Simulation and experimental results of our approach are compared with the recent on-chip interconnection approaches that supports our claim.

SWIFTNoC

On-chip communication is widely considered to be one of the major performance bottlenecks in contemporary chip multiprocessors (CMPs). With recent advances in silicon nanophotonics, photonics-based network-on-chip (NoC) architectures are being considered as a viable solution to support communication in future CMPs as they can enable higher bandwidth and lower power dissipation compared to traditional electrical NoCs. In this article, we present SwiftNoC , a novel reconfigurable silicon-photonic NoC architecture that features improved multicast-enabled channel sharing, as well as dynamic re-prioritization and exchange of bandwidth between clusters of cores running multiple applications, to increase channel utilization and system performance. Experimental results show that SwiftNoC improves throughput by up to 25.4× while reducing latency by up to 72.4% and energy-per-bit by up to 95% over state-of-the-art solutions.

High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router

In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port – named Routing Modification port – into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC/C++, simulated and verified within a 2D mesh 5×5 network platform. In normal communication mode, the static XY routing algorithm is used while the West-First algorithm with a proposed prohibited router surrounding technique is applied in reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes as well as with other works.

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

In this paper, an efficient application mapping approach is proposed for the co-optimization of reliability, communication energy, and performance (CoREP) in network-on-chip (NoC)-based reconfigurable architectures. A cost model for the CoREP is developed to evaluate the overall cost of a mapping. In this model, communication energy and latency (as a measure of performance) are first considered in energy latency product (ELP), and then ELP is co-optimized with reliability by a weight parameter that defines the optimization priority. Both transient and intermittent errors in NoC are modeled in CoREP. Based on CoREP, a mapping approach, referred to as priority and ratio oriented branch and bound (PRBB), is proposed to derive the best mapping by enumerating all the candidate mappings organized in a search tree. Two techniques, branch node priority recognition and partial cost ratio utilization, are adopted to improve the search efficiency. Experimental results show that the proposed approach achieves significant improvements in reliability, energy, and performance. Compared with the state-of-the-art methods in the same scope, the proposed approach has the following distinctive advantages: 1) CoREP is highly flexible to address various NoC topologies and routing algorithms while others are limited to some specific topologies and/or routing algorithms; 2) general quantitative evaluation for reliability, energy, and performance are made, respectively, before being integrated into unified cost model in general context while other similar models only touch upon two of them; and 3) CoREP-based PRBB attains a competitive processing speed, which is faster than other mapping approaches.

Reconfigurable Adaptive Routing Buffer Design for Scalable Power Efficient Network On Chip

The layout density of integrated circuits on a single chip has led to the reduced size at sub-micron scales of VLSI design. The System on Chip (SOC) design has few challenges, such as latency, power, area and reliable data transmission among sub-systems interconnected on a single chip. Network on Chip (NOC) is a subset of SOC which accomplishes on-chip communication process. The performance of NOC architecture is significantly affected by power and area. This research work has focused on a new low power reconfigurable NOC architecture with repeaters between the routers. The repeater enables zero buffers between the interlink routers. It works on the principles of store and forward process. The proposed architecture is implemented using mesh network topology. The simulated results of new architecture have shown a reduction in power dissipation by 56% and reduction in on chip area by as much as 60%. Keywords: Network on Chip (NOC), Reconfigurable Architecture, System on Chip (SOC)

Leveraging dark silicon to optimize networks-on-chip topology

This paper presents a reconfigurable network-on-chip (NoC) for many-core chip multiprocessors (CMPs) in the dark silicon era, where a considerable part of high-end chips cannot be powered up due to the power and bandwidth walls. Core specialization, which trades off the cheaper silicon area with energy-efficiency, is a promising solution to the dark silicon challenge. This approach integrates a selection of many diverse application-specific cores into a single many-core chip. Each application then activates those cores that best match its processing requirements. Since active cores may not always form a contiguous active region in the chip, such a partially active many-core CMP requires some special on-chip communication support to optimize NoC parameters for the current set of active cores. In this paper, we propose a reconfigurable NoC that leverages inactive routers of a many-core chip to customize the topology for active cores. In this design, routers of the dark part of the chip are used as bypass switches that can set up virtual long links between distant active nodes in the network. Our experimental results show considerable reduction in NoC energy consumption and latency.

Application-based dynamic reconfiguration in optical network-on-chip

We propose a new optical reconfigurable Network-on-Chip (NoC), named ReFaT ONoC (Reconfigurable Flat and Tree Optical NoC). ReFaT is a dynamically reconfigurable architecture, which customizes the topology and routing paths based on the application characteristics. ReFaT, as an all-optical NoC, routes optical packets based on their wavelengths. For this purpose, we propose a novel architecture for the optical switch, which eliminates the need for optical resource reservation, and thus avoids the corresponding latency and area overheads. As a key idea for dynamic reconfiguration, each application is mapped to a specific set of wavelengths and utilizes its dedicated routing algorithm. We compare the proposed reconfigurable optical NoC with traditional electrical NoCs, as well as non-reconfigurable optical NoCs in terms of data transmission delay, power consumption, and energy dissipation. The simulation results show that on average, ReFaT reduces power and energy consumption by 54.75% and 40%, respectively, compared to the non-reconfigurable ONoC.

Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip

Crosstalk interferences and high dynamic power consumption in a network-on-chip (NoC) are two increasingly problematic design issues. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic power. However, data codecs have different overheads in terms of area and performance, and varying capabilities in reducing crosstalk and dynamic power. To adapt to the wide range of processing requirements incurred by applications and operating environments, a reasoning and learning (REAL) framework is proposed for a reconfigurable NoC. REAL dynamically investigates the tradeoffs among reliability, dynamic power reduction, performance, and hardware resource usages to configure the reconfigurable NoC with an appropriate data codec at runtime. As a proof of concept, a 3 × 3 reconfigurable NoC was implemented on Xilinx Virtex-4 field-programmable gate array, which required 8.2% lesser number of slices compared with a conventional NoC. Experiments show that at the same overheads of performance and hardware resources the reconfigurable NoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption.

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption

To solve two increasingly problematic issues, namely crosstalk interferences and wire power consumption, in a Network-on-Chip (NoC), Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) is proposed. It includes a novel reconfigurable NoC design, four data encoding strategies, and an intelligent REasoning And Learning (REAL) framework for encoding strategy selection. Instead of pre-integrating all encoding strategies into a NoC at design time, REAL can configure PRESSNoC with an appropriate encoding method at run-time. Compared to baseline NoCs that use a fixed encoding method, the average benefit to overhead ratio of the PRESSNoC is greater by 88%, 39%, and 277%, at the interference, application, and system levels, respectively. Experiments show that at the same overheads of performance and hardware resources PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption.

Implementation and Evaluation of Skip-Links

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.