Reconfigurable Microarchitectures Research Articles

A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications

This article proposes reconfigurable maximum a posteriori (MAP) decoding algorithm which operates in multiple radix modes to hard decode the information bits with variable throughput by consuming constant power. Subsequently, a new digital decoder-architecture for this MAP decoding algorithm has been designed that operates in radix-2/4/8 modes. Furthermore, reconfigurable microarchitectures of state-metric and logarithmic-likelihood-ratio (LLR) computation units are presented in this article. Performance analyses of the proposed algorithm have been performed in additive-white Gaussian-noise (AWGN) channel environment where it achieved a bit-error-rate (BER) of 10−4 at a signal-to-noise ratio (SNR) of 5 dB. Suggested multiple-radix MAP-decoder is fabricated in united-microelectronics-corporation (UMC) 130-nm-CMOS technology node and it occupies die and core areas of 2.35 and 1.28 mm2, respectively, operating at a maximum clock frequency of 204 MHz. This MAP decoder ASIC-chip delivers throughputs of 201, 403, and 605 Mb/s while operating in radix-2, 4 and 8 modes, respectively, consuming a total power of 92 mW. Our chip achieves 0.15 nJ/bit of energy efficiency, which is 30% better than the most energy-efficient implementation from literature. Likewise, it delivers 39% higher throughput and $70\times $ better area-efficiency than the state-of-the-art work.

Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing Utilization

in this article, a Reconfigurable Microarchi- tecture-based PMDC prototype is developed with the help of dynamic pipeline stages. The Reconfigurable Microarchitecture is intended for the Internet of Things (IoT) edge level computing utilization purposes. This microarchitecture is implemented using a reconfigurable computing system with the help of an FPGA board. The reconfigurable microarchitecture is used as a feedback circuit of the PMDC motor to come out with a developed speed control prototype that can be sufficiently integrated with IoT technology. The number of pipeline stages will dynamically change as per user speed requirements. Several methods of speed measurement are tested using different pipeline structures to find out an appropriate method for the IoT edge level. Resource utilization, throughput and latency for those methods are analyzed. Additionally, the reconfigurable microarchitecture gives dynamic power consumption which more suitable for IoT edge level computations. The Real-Time behavior of the developed prototype is carried out with a pseudo-random binary sequence (PRBS) test for its system identification, a particle swarm optimization (PSO) technique for its optimal controller design and edge level computations for its IoT integration procedure.

An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications

Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting requirements. This paper introduces a reconfigurable micro-architectural level technique that allows a Reduced Instruction Set Computing (RISC) processor to support IoT applications with different performance and energy trade-off requirements. The processor can be reconfigured into either multi-cycle execution mode (low computational speed with low dynamic power consumption) or pipeline execution mode (high computational speed at the expense of high dynamic power), based on dynamic workload characteristics in IoT applications. Switching between modes is accomplished by exploiting the partial reconfiguration (PR) feature offered by the recent advancements in modern FPGAs. A RISC processor was designed based on the proposed micro-architectural level technique and implemented on FPGA as IoT sensor node. Experimental results demonstrate that the proposed technique with reconfigurable micro-architecture is able to significantly reduce the dynamic energy consumption, compared to conventional multi-cycle and pipeline only micro-architectures, while allowing better performance-energy trade-off in IoT applications.

Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling

This article introduces a systematic methodology to design microarchitectures that are reconfigurable down to the pipeline stage. Reconfigurable microarchitectures were showed to provide significant energy improvements in accelerators under wide-voltage scaling. However, prior art is based on ad hoc techniques that limit their applicability, without addressing the challenge of enabling general design flows for reconfigurable microarchitectures. The proposed methodology introduces the unprecedented capability of translating a conventional fixed microarchitecture into a reconfigurable one. The methodology relies on commercial EDA tools, which are integrated into a design flow through the manipulation of the gate-level netlist via a set of graph algorithms. The proposed methodology is shown to be architecture-agnostic, fully automated, and applicable to designs that are either developed at the register transfer level (RTL), or provided by third-party soft IP vendors. Ultimately, the proposed methodology allows to add microarchitectural adjustment as a run-time knob to augment the energy benefits of wide-voltage scaling. Reconfiguration is shown to improve the energy efficiency by up to 35% beyond the conventional dynamic voltage frequency scaling (DVFS), through the analysis of various test vehicles.

High-level synthesis system based on hybrid reconfigurable microarchitecture

Subject of Research. The paper presents research of state-of-the-art methods of real-time hardware / software systems development based on FPGAs and SoCs. High-level synthesis system based on the hybrid reconfigurable NISC/TTA microarchitecture is proposed. Method. The work is based on analysis and synthesis of computer architectures and their design methods within Model-Driven Engineering, High-Level Synthesis and Hardware/Software Codesign methodologies. Main Results. Analysis of academic and commercial tools for development of hardware/software systems based on FPGAs and SoCs is performed. The key factors are determined limiting the wide introduction of high-level synthesis tools in industry. The ideology and architecture of the high-level synthesis system are developed on the basis of the original reconfigurable NISC/TTA microarchitecture. The prototype of the considered EDA system is developed. The synthesis tool and the synthesis process control interface are among the most valuable outcomes and give the possibility to explore the results of synthesis decisions made by the tool, and control the process either manually or automatically. The visualization interface of the target computational process is implemented that allows for effective representation of its multi-level organization. The end-to-end testing system is developed enabling verification of compliance between a synthesized system and its functional model. Practical Relevance. The tools implemented as part of the CAD prototype have made the synthesis process transparent and manageable for the designer and demonstrated the possibility of finding compromise design solutions in semi-automatic mode. We managed to control flexibly heuristics in the synthesizer operation, not only reducing design iterations, but also making the process convergent in principle, which is not provided by alternative technologies in many cases. NISC/TTA microarchitecture played an important role in this process. Solution of a number of test problems has shown that this design platform can be recommended for implementation of control algorithms in real-time systems and for the application in system dynamics modeling.

Design of Processors with Reconfigurable Microarchitecture

Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.