Reconfigurable Interconnection Network Research Articles

Hardware Trojan Attacks on the Reconfigurable Interconnections of Field-Programmable Gate Array-Based Convolutional Neural Network Accelerators and a Physically Unclonable Function-Based Countermeasure Detection Technique.

Convolutional neural networks (CNNs) have demonstrated significant superiority in modern artificial intelligence (AI) applications. To accelerate the inference process of CNNs, reconfigurable CNN accelerators that support diverse networks are widely employed for AI systems. Given the ubiquitous deployment of these AI systems, there is a growing concern regarding the security of CNN accelerators and the potential attacks they may face, including hardware Trojans. This paper proposes a hardware Trojan designed to attack a crucial component of FPGA-based CNN accelerators: the reconfigurable interconnection network. Specifically, the hardware Trojan alters the data paths during activation, resulting in incorrect connections in the arithmetic circuit and consequently causing erroneous convolutional computations. To address this issue, the paper introduces a novel detection technique based on physically unclonable functions (PUFs) to safeguard the reconfigurable interconnection network against hardware Trojan attacks. Experimental results demonstrate that by incorporating a mere 0.27% hardware overhead to the accelerator, the proposed hardware Trojan can degrade the inference accuracy of popular neural network architectures, including LeNet, AlexNet, and VGG, by a significant range of 8.93% to 86.20%. The implemented arbiter-PUF circuit on a Xilinx Zynq XC7Z100 platform successfully detects the presence and location of hardware Trojans in a reconfigurable interconnection network. This research highlights the vulnerability of reconfigurable CNN accelerators to hardware Trojan attacks and proposes a promising detection technique to mitigate potential security risks. The findings underscore the importance of addressing hardware security concerns in the design and deployment of AI systems utilizing FPGA-based CNN accelerators.

A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing

The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable interconnection network. However, the mastering of low-level microarchitectural details involved in the programming of such massively parallel platforms becomes too cumbersome, which limits their adoption in many applications. Thus, there is a dire need for an approach to produce high-performance scalable implementations that harness the computational resources of the emerging reconfigurable platforms. This article addresses the grand challenge of accessibility of these diverse reconfigurable platforms by suggesting the use of a high-level language, occam-pi, and developing a complete design flow for building, compiling, and generating machine code for heterogeneous coarse-grained hardware. We have evaluated the approach by implementing complex industrial case studies and three common signal processing algorithms. The results of the implemented case studies suggest that the occam-pi language-based approach, because of its well-defined semantics for expressing concurrency and reconfigurability, simplifies the development of applications employing runtime reconfigurable devices. The associated compiler framework ensures portability as well as the performance benefits across heterogeneous platforms.

An FPGA-Based Reconfigurable Mesh Many-Core

The reconfigurable mesh is a parallel model of computation, which exploits a massive amount of rather simple processing elements connected through a reconfigurable interconnection network. During the last decades, the model received strong interest and many researchers have devised algorithms for it. However, most of this work focuses on theoretical aspects. Due to some idealistic modeling assumptions only a few attempts have been made to implement the model and to study the practical use of reconfigurable meshes. In this paper, we leverage the reconfigurable mesh model to study potential architectures and programming models for future many-cores. We design a reconfigurable mesh in form of a scalable soft core array with a reconfigurable interconnect and implement it on FPGA technology in order to create a prototype platform. We present an overall hardware/software tool flow for generating and programming reconfigurable mesh prototypes. The new language ARMLang and a corresponding compiler facilitate the programming of the massively parallel processor arrays. To our knowledge, this work is the first practical study of word-level reconfigurable meshes. To analyze the performance of our implementation we study four algorithmic kernels from the application domains arithmetic, sorting, graph algorithms and imaging. For each kernel, we devise a reconfigurable mesh program in ARMLang, compile it to our soft core array and measure its runtime depending on the mesh size. Then, we compare the runtimes to two sequential implementations of the algorithms, which are executed on two single core systems. The results show that many-cores leveraging the reconfigurable mesh model can efficiently use a vast number of processing elements and that, for the chosen algorithms, they come close to optimally parallelized programs.

Design Automation Framework for Reconfigurable Interconnection Networks

A reconfigurable interconnection network (RIN) is a custom-designed on-chip switching network yielding routing solutions for a pre-given set of applications. Like field programmable gate array (FPGA) routing networks, the RIN is used to make reconfigurable interconnections among functional blocks. Unlike FPGAs, the network topology of a RIN is irregular as it is designed for a given set of routing requirements and optimized for the area cost subject to given delay constraints. In this paper, we propose an automatic design scheme for RINs, including routing specification formulation, graph modelings, network topology designs, routing algorithms and multiplexer-based network circuit implementation. The choice of the design scheme is based on the existing routing network design practices and research, which give feasible solutions. Our scheme is to optimize the designs with the choice of design parameters. A computer-aided design (CAD) tool is developed based on the design scheme, which takes a set of routing requirements as input and produces the corresponding RIN network topology and network circuit in hardware description language format. We present the area costs of various RINs generated by the CAD tool subject to delay constraints, and illustrate the RIN design scheme with a reconfigurable multistream video system.

A MITE-Based Translinear FPAA

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. An FPAA built using Multiple Input Translinear Elements (MITEs) has been designed, fabricated in 0.35 μ m CMOS, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, RMS-to-DC converters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors

Interconnection networks for multicore processors are traditionally designed to serve a diversity of workloads. However, different workloads or even different execution phases of the same workload may benefit from different interconnect configurations. In this paper, we first motivate the need for workload-adaptive interconnection networks. Subsequently, we describe an interconnection network framework based on reconfigurable switches for use in medium-scale (up to 32 cores) shared memory multicore processors. Our cost-effective reconfigurable interconnection network is implemented on a traditional shared bus interconnect with snoopy-based coherence, and it enables improved multicore performance. The proposed interconnect architecture distributes the cores of the processor into clusters with reconfigurable logic between clusters to support workload-adaptive policies for inter-cluster communication. Our interconnection scheme is complemented by interconnect-aware scheduling and additional interconnect optimizations which help boost the performance of multiprogramming and multithreaded workloads. We provide experimental results that show that the overall throughput of multiprogramming workloads (consisting of two and four programs) can be improved by up to 60% with our configurable bus architecture. Similar gains can be achieved also for multithreaded applications as shown by further experiments. Finally, we present the performance sensitivity of the proposed interconnect architecture on shared memory bandwidth availability.

Predicting reconfigurable interconnect performance in distributed shared-memory systems

Reconfigurable interconnection networks have been shown to benefit performance in distributed shared-memory multiprocessor machines. Usually, performance measurements for these networks require large numbers of slow full-system simulations, making design-space exploration a cumbersome and time-consuming task. In this paper, we present a prediction model for the performance of a reconfigurable network, based on a single full-system simulation and a much shorter, per parameter set post-processing phase. We provide simulation results establishing the relative accuracy of the technique and analyze the impact of several assumptions that were made. With our method, a quick evaluation of a large range of parameters is now possible, allowing the designer to make well-founded design trade-offs.

Decomposition design theory and methodology for arbitrary-shaped switch boxes

We consider the optimal design problem for arbitrary-shaped switch box, (r1...rk) which r, terminals are located on side i for i= 1...k and programmable switches are joining pairs of terminals from different sides. Previous investigations on switch box designs mainly focused on regular switch boxes in which all sides have the same number of terminals. By allowing different numbers of terminals on different sides, irregular switch boxes are more general and flexible for applications such as customized FPGAs and reconfigurable interconnection networks. The optimal switch box design problem is to design a switch box satisfying the given shape and routing capacity specifications with the minimum number of switches. We present a decomposition design method for a wide range of irregular switch boxes. The main idea of our method is to model a routing requirement as a nonnegative integer vector satisfying a system of linear equations and then derive a decomposition theory of routing requirements based on the theory of systems of linear Diophantine equations. The decomposition theory makes it possible to construct a large irregular switch box by combining small switch boxes of fixed sizes. Specifically, we can design a family of hyperuniversal (universal) (u-d + c)-SBs with B(h-) switches, where d and c are constant vectors and w is a scalar. We illustrate the design method by designing a class of optimal hyperuniversal irregular 3-sided switch boxes and a class of optimal rectangular universal switch boxes. Experimental results on the rectangular universal switch boxes with the VPR router show that the optimal design of irregular switch boxes does pay off.

A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilities of scan test cubes has been developed to reorder scan cells. Experimental results demonstrate that the proposed CRIN BIST technique reduces test time by 35% and the storage requirement by 39% in comparison with previous work.

Reducing Control Latency in Distributed Shared-Memory Multiprocessor Systems Using Fuzzy Logic Prediction

Communication latency is a major limiting factor for scalability in distributed shared-memory multiprocessor systems. It can be generally reduced by predicting the communication traffic in a system connected through a reconfigurable interconnection network. The State Sequence Routing (SSR) control-based algorithm uses a set of predicted paths to do an anticipatory reconfiguration for the interconnection network (IN) in such a way as to include the set of predicted paths in the current state sequence. By reducing the control latency and thus the overall execution time of a parallel application, we can increase the network size and therefore improve the scalability. In this article we use a fuzzy inference system (FIS) to perform online prediction of the paths between processors and memory units. The fuzzy system uses as input the memory access patterns across a set of time-windows to predict the communication paths within the next time window. Hence, the prediction is based on the locality inherent in the memory access patterns for all processors across the network. To investigate the effectiveness of our approach, we perform several simulation experiments using a program-driven simulator. Based on the results of experiments, our algorithm reduces the communication latency and thus the overall execution time according to the locality inherent in the communication traffic across the network using as little resources as possible in terms of the length of the state sequence router and the size of the rule base.

Reducing Control Latency in Distributed Shared-Memory Multiprocessor Systems using Fuzzy Logic Prediction

AbstractCommunication latency is a major limiting factor for scalability in distributed shared-memory multiprocessor systems. It can be generally reduced by predicting the communication traffic in a system connected through a reconfigurable interconnection network. The State Sequence Routing (SSR) control-based algorithm uses a set of predicted paths to do an anticipatory reconfiguration for the interconnection network (IN) in such a way as to include the set of predicted paths in the current state sequence. By reducing the control latency and thus the overall execution time of a parallel application, we can increase the network size and therefore improve the scalability. In this article we use a fuzzy inference system (FIS) to perform online prediction of the paths between processors and memory units. The fuzzy system uses as input the memory access patterns across a set of time-windows to predict the communication paths within the next time window. Hence, the prediction is based on the locality inherent...

Test Set Embedding for Deterministic BIST Using a Reconfigurable Interconnection Network

We present a new approach for deterministic built-in self-test (BIST) in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase shifter that is typically used in pseudorandom BIST to reduce correlation between the test data bits that are fed into the scan chains. The connections between the linear-feedback shift-register (LFSR) and the scan chains can be dynamically changed (reconfigured) during a test session. In this way, the RIN is used to match the LFSR outputs to the test cubes in a deterministic test set. The control data bits used for reconfiguration ensure that all the deterministic test cubes are embedded in the test patterns applied to the CUT. The proposed approach requires very little hardware overhead, only a modest amount of CPU time, and fewer control bits compared to the storage required for reseeding techniques or for hybrid BIST. Moreover, as a nonintrusive BIST solution, it does not require any circuit redesign and has minimal impact on circuit performance.

A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm/spl times/6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-/spl mu/m 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network.

Performance evaluation of massively parallel processing architectures with three-dimensional optical interconnections

We evaluate the performance of three-dimensional optoelectronic computer architectures on the basis of basic database operations and parallel benchmark algorithms for numerical computations. We show that the select and the join database operations can be performed much faster with an optical interconnection network. Also, optoelectronic architectures can perform the fast Fourier transform and sorting benchmarks orders of magnitude faster than electronic supercomputers. An architecture with an adequately fast reconfigurable interconnection network can perform the conjugate-gradient benchmark faster than all parallel supercomputers, but its performance is not as impressive when a fixed network is used. In the case of the multigrid benchmark the three-dimensional optoelectronic architecture also can outperform the best parallel supercomputers.

High-speed 2-D convolution with a custom computing machine

Custom computing machines, a class of computational platforms consisting of reconfigurable functional units with reconfigurable interconnection networks, provide a middle-ground between special-purpose hardware, which provide high execution speed, and general-purpose computers, which offer flexibility. The Splash-2 system, one such custom computing machine, is an experimental platform for complex computations requiring the high speed of special-purpose hardware. The reconfigurability and modularity of Splash-2, along with automated synthesis tools, allow for rapid, staged development of applications. This paper demonstrates the applicability of Splash-2 to the image-processing area and gives an introduction to the programming environment used in developing applications. An example image-processing application based upon two-dimensional convolution is described and the operating procedures of custom computing machines are presented. Also presented are the details of directly implementing two-dimensional convolution in a straight-forward, systolic fashion in reconfigurable hardware.

The REFINE multiprocessor — theoretical properties and algorithms

A reconfigurable interconnection network based on a multi-ring architecture called REFINE is described. REFINE embeds a single 1-factor of the Boolean hypercube in any given configuration. The mathematical properties of the REFINE topology and the hardware for the reconfiguration switch are described. The REFINE topology is scalable in the sense that the number of interprocessor communication links scales linearly with network size whereas the network diameter scales logarithmically with network size. Primitive parallel operations on the REFINE topology are described and analyzed. These primitive operations could be used as building blocks for more complex parallel algorithms. A large class of algorithms for the Boolean n-cube which includes the FFT and the Batcher's bitonic sort is shown to map efficiently on the REFINE topology. The REFINE multiprocessor is shown to offer a cost-effective alternative to the Boolean n-cube multiprocessor architecture without substantial loss in performance.

Proteus: A reconfigurable computational network for computer vision

The Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs a hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1024 RISC processors. The processors use one megabyte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates, and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. >

Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Theta (log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated. >

Reduction operations on a distributed memory machine with a reconfigurable interconnection network

Performing reduction operations with distributed memory machines whose interconnection networks are reconfigurable is considered. The focus is on machines whose interconnection graph can be configured as any graph of maximum degree d. The best way of interconnecting the p processors as a function of p,d and some problem- and machine-dependent parameters that characterize the ratio communication/arithmetic for the reduction operation are discussed. Experiments on transputer-based networks are in good accordance with the theoretical results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Electro-optic hologram generation on spatial light modulators

An iterative method for generating holograms on spatial light modulators is based on measuring the reconstructed complex image and on-line correction of the hologram. Apart from recording complex amplitude distributions, the new procedure may become a useful tool for applications such as adaptive optics and reconfigurable interconnection networks.