Reducing Control Latency in Distributed Shared-Memory Multiprocessor Systems Using Fuzzy Logic Prediction

Abstract

Communication latency is a major limiting factor for scalability in distributed shared-memory multiprocessor systems. It can be generally reduced by predicting the communication traffic in a system connected through a reconfigurable interconnection network. The State Sequence Routing (SSR) control-based algorithm uses a set of predicted paths to do an anticipatory reconfiguration for the interconnection network (IN) in such a way as to include the set of predicted paths in the current state sequence. By reducing the control latency and thus the overall execution time of a parallel application, we can increase the network size and therefore improve the scalability. In this article we use a fuzzy inference system (FIS) to perform online prediction of the paths between processors and memory units. The fuzzy system uses as input the memory access patterns across a set of time-windows to predict the communication paths within the next time window. Hence, the prediction is based on the locality inherent in the memory access patterns for all processors across the network. To investigate the effectiveness of our approach, we perform several simulation experiments using a program-driven simulator. Based on the results of experiments, our algorithm reduces the communication latency and thus the overall execution time according to the locality inherent in the communication traffic across the network using as little resources as possible in terms of the length of the state sequence router and the size of the rule base.