Reconfigurable Interconnection Research Articles

Switched holograms for reconfigurable optical interconnection: demonstration of a prototype device

We report the construction of a device intended for programmable optical interconnection of multiple processors in a highly parallel computer. This device, the Holoswitch, is based on an array of optical switches (liquid crystal polarization switches and polarizing beam splitters), which direct a set of optical beams toward any of a selection of holograms. Each hologram, when selected, deflects the input beams toward an output array with any desired prerecorded permutation. The prototype device has nine different interconnection patterns recorded on a single 10-x12.7-cm DCG hologram. We have recorded permutation patterns with up to 64 optical channels in an area of 4 cm(2).

A synthesis algorithm for reconfigurable interconnection networks

The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if its topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. It is shown how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by the algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average-case performance prediction and confirm that, on the average, the optimum topologies are generated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sprint - The Systolic Processor with a Reconfigurable Interconnection Network of Transputers

The Systolic Processor with a Reconfigurable Interconnection Network of Transputers (SPRINT) is a sixty-four-processor multiprocessor developed at Lawrence Livermore National Laboratory for experimentally evaluating systolic algorithms and architectures. This paper describes the architecture of the SPRINT and several algorithms which have been executed on it.