Reconfigurable Interconnection Research Articles

A dynamically reconfigurable interconnect for array processors

Reconfigurability of processor arrays is important due to two reasons (1) to efficiently execute different algorithms and (2) to isolate faulty processors. An array processor that is reconfigurable by the user any number of times to yield a different topology or to isolate faults is envisaged in this paper. The system has a host or controller that broadcasts a command to the interconnect to configure itself into a particular fashion. The interconnect uses static-RAM programming technology and can be programmed to different configurations by sending a different set of bits to the configuration random access memory (RAM) in the interconnect. We present three designs reconfigurable into array, ring, mesh, or Illiac mesh topologies. The first design provides no redundancy or fault tolerance. The second design is capable of graceful degradation by bypassing faulty elements. The third design is capable of graceful degradation by rerouting. The details of the interconnect and the configuration RAM contents for typical configurations are illustrated. It is seen that reconfigurable interconnect results in a highly reconfigurable or polymorphic computer.

Performance evaluation of massively parallel processing architectures with three-dimensional optical interconnections

We evaluate the performance of three-dimensional optoelectronic computer architectures on the basis of basic database operations and parallel benchmark algorithms for numerical computations. We show that the select and the join database operations can be performed much faster with an optical interconnection network. Also, optoelectronic architectures can perform the fast Fourier transform and sorting benchmarks orders of magnitude faster than electronic supercomputers. An architecture with an adequately fast reconfigurable interconnection network can perform the conjugate-gradient benchmark faster than all parallel supercomputers, but its performance is not as impressive when a fixed network is used. In the case of the multigrid benchmark the three-dimensional optoelectronic architecture also can outperform the best parallel supercomputers.

Reconfigurable interconnection using fixed regional angular volume holograms in photorefractive materials

We demonstrate a scheme of reconfigurable optical interconnections using angular multiple holograms in a photorefractive medium. The conjugation light paths of three regular interconnect configurations are stored and fixed. Real-time two-wave mixing with the forward read-out technique combined with a special optical imaging system is employed to achieve the incident angle of the input beam as changeable but the position has no shift. Issues about ability of reconfiguration, cross-over and energy efficiency are discussed theoretically. A proof-of-principle experiment is also presented.

Reconfigurable time-steered array-antenna beam former

We present and analyze a hardware-optimized technique that provides true-time-delay steering for broadband two-dimensional array-antenna applications. The technique improves on previous approaches by the reduction of the two-dimensional beam-former architecture complexity, by the provision of flexibility in time-delay unit selection, and by the potential reduction of optical loss. The technique relies on a one-dimensional bank of time-delay units to form the required time-delay gradient for proper off-broadside angle steering. A reconfigurable optical interconnection fabric is used to reassign dynamically the connections between the time-delay units and individual array elements of a two-dimensional array to effect the proper steering angle along the off-broadside cone.

Experimental demonstration of a four-plane 2-D multiple-wavelength optical interconnection using integrated VCSEL arrays and MQW/DBR detectors

We experimentally demonstrate a four-plane two-dimensional (2-D) wavelength-division multiplexed (WDM) optical interconnection using integrated multiple-wavelength WDM transmitting VCSEL arrays and three-wavelength-selective detector arrays. The detector planes employ multiquantum-well (MQW) detector arrays, with the middle plane being a novel channel-dropping detector with a single mirror resonant cavity. This middle plane provides superior wavelength selectivity thereby reducing crosstalk from the shorter and longer wavelength channels. Reconfigurable and simultaneous WDM interconnections between planes are demonstrated at 155 Mb/s.

Microoptical elements for single mode fibre arrays free-space interconnections

The purpose of this paper is to investigate the performance of microoptics for telecommunication systems using free-space interconnects. This concerns mainly distribution or switching and routing tasks. In order to evaluate the interconnection capability of free-space microoptics, we impose severe conditions on the interconnects. These conditions correspond to the use of single mode fibre arrays at both the input and the output systems. This point is shown to become very critical when dealing with optical switches involving reconfigu-rable links. These points are illustrated by two examples : one with fixed and the other with reconfigurable interconnects but both using arrays of microoptical elements.

Collisional interactions of vectorial spatial solitary waves in type II frequency-doubling media

We present the results of an extensive numerical investigation of the interactions of vectorial spatial solitary waves propagating in bulk media that exhibit a quadratic optical nonlinearity. Various features, including beam coalescence, steering, crossing, and repulsion, indicate the potential applications of these phenomena in available birefringent χ(2) crystals. In the framework of all-optical reconfigurable interconnects, phase- and intensity-based control schemes are discussed and compared.

Simulating Shared Memory in Real Time: On the Computation Power of Reconfigurable Architectures

We consider randomized simulations of shared memory on a distributed memory machine (DMM) where the n processors and the n memory modules of the DMM are connected via a reconfigurable architecture. We first present a randomized simulation of a CRCW PRAM on a reconfigurable DMM having a complete reconfigurable interconnection. It guarantees delay O (log * n ), with high probability. Next we study a reconfigurable mesh DMM (RM-DMM). Here the n processors and n modules are connected via an n × n reconfigurable mesh. It was already known that an n × m reconfigurable mesh can simulate in constant time an n -processor CRCW PRAM with shared memory of size m . In this paper we present a randomized step by step simulation of a CRCW PRAM with arbitrarily large shared memory on an RM-DMM. It guarantees constant delay with high probability, i.e., it simulates in real time. Finally we prove a lower bound showing that size Ω ( n 2 ) for the reconfigurable mesh is necessary for real time simulations.

Parallel 3-dimensional optical interconnections using liquid crystal devices for B-ISDN electronic switching systems

In this paper, we propose a system design for a parallel 3-dimensional optical interconnection network utilizing variable grating mode liquid crystal devices (VGM LCD's) which are optical transducers capable of performing intensity-to-spatial-frequency conversion. The proposed system performs real-time, reconfigurable, but blocking and nonbroadcasting 3-dimensional optical interconnections. The operating principles of the 3-D optical interconnection network are described, and some of the fundamental limitations are addressed. The system presented in this paper can be directly used as a configuration of switching elements for the 2-D optical perfect-shuffle dynamic interconnection network, as well as for a B-ISDN photonic switching system.

Experimental demonstration of reconfigurable and simultaneous wavelength-division-multiplexed multiple-plane optical interconnections

We report the first experimental demonstration of using wavelength-division-multiplexing and wavelength-selective-detection to facilitate either reconfigurable or simultaneous optical interconnections between one source plane and many detector planes. We show the 10/sup -9/ BER, 155 Mb/s transmission and detection of three different wavelength-multiplexed signals at three detector planes. The reconfigurable interconnection is established with a wavelength separation of 10 nm, and the simultaneous interconnection is established with a wavelength separation of 43 nm.

High-speed 2-D convolution with a custom computing machine

Custom computing machines, a class of computational platforms consisting of reconfigurable functional units with reconfigurable interconnection networks, provide a middle-ground between special-purpose hardware, which provide high execution speed, and general-purpose computers, which offer flexibility. The Splash-2 system, one such custom computing machine, is an experimental platform for complex computations requiring the high speed of special-purpose hardware. The reconfigurability and modularity of Splash-2, along with automated synthesis tools, allow for rapid, staged development of applications. This paper demonstrates the applicability of Splash-2 to the image-processing area and gives an introduction to the programming environment used in developing applications. An example image-processing application based upon two-dimensional convolution is described and the operating procedures of custom computing machines are presented. Also presented are the details of directly implementing two-dimensional convolution in a straight-forward, systolic fashion in reconfigurable hardware.

The REFINE multiprocessor — theoretical properties and algorithms

A reconfigurable interconnection network based on a multi-ring architecture called REFINE is described. REFINE embeds a single 1-factor of the Boolean hypercube in any given configuration. The mathematical properties of the REFINE topology and the hardware for the reconfiguration switch are described. The REFINE topology is scalable in the sense that the number of interprocessor communication links scales linearly with network size whereas the network diameter scales logarithmically with network size. Primitive parallel operations on the REFINE topology are described and analyzed. These primitive operations could be used as building blocks for more complex parallel algorithms. A large class of algorithms for the Boolean n-cube which includes the FFT and the Batcher's bitonic sort is shown to map efficiently on the REFINE topology. The REFINE multiprocessor is shown to offer a cost-effective alternative to the Boolean n-cube multiprocessor architecture without substantial loss in performance.

Real-Time Reconfigurable Interconnections for Parallel Optical Processing

In this letter we describe the advantages of a dynamic optical interconnection system for parallel information processing applications. The system is based on a liquid crystal television which acts as a binary phase-only spatial light modulator. We describe example algorithms where reconfigurable interconnects would be useful and present results of several interconnection topologies which have been implemented.

Proteus: A reconfigurable computational network for computer vision

The Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs a hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1024 RISC processors. The processors use one megabyte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates, and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. >

Dynamics of the diffraction efficiency of holograms regenerated periodically in bacteriorhodopsin

An analysis is made of the problem of switching of a large number of information channels by an array of reconfigurable holograms formed in a dynamic photocarrier. A report is given of an experimental study of the dynamics of the diffraction efficiency of holograms regenerated periodically in bacteriorhodopsin. An experimental prototype of a system of reconfigurable interconnects is described.

Node-based reconfigurable volume interconnection 1 Principles and optical design

We present a general-purpose three-dimensional interconnection network that models various parallel operations between two data planes. This volume interconnection system exhibits reconfigurable capabilities because of parallel and externally weighted interconnection modules, called nodes. We propose a generic optical implementation based on the cascading of two planar hologram arrays, coupled with a bistable optically addressed spatial light modulator. The role of this component is discussed in terms of energy regeneration and spatial cross-talk limitation. As an example, a binary matrix-matrix multiplier is implemented that uses a ferroelectric liquid-crystal light valve.

R2M: A RECONFIGURABLE REWRITE MACHINE

Term rewriting is a popular computational paradigm for symbolic computations such as formula manipulation, theorem proving and implementations of nonprocedural programming languages. In rewriting, the most demanding operation is repeated simplification of terms by pattern matching them against rewrite rules. We describe a parallel architecture, R2M, for accelerating this operation. R2M can operate either as a stand-alone processor using its own memory or as a backend device attached to a host using the host’s main memory. R2M uses only a fixed number (independent of input size) of processing units and fixed capacity auxiliary memory units, yet it is capable of handling variable-size rewrite rules that change during simplification. This is made possible by a simple and reconfigurable interconnection present in R2M. Finally, R2M uses a hybrid scheme that combines the ease, and efficiency of parallel pattern matching using the tree representation of terms, and the naturalness of their dag representation for replacements.

Generation of reconfigurable interconnections with a two-dimensional acousto-optic deflector

We detail the technical considerations for producing reconfigurable spot patterns with an integrated two-dimensional acousto-optic deflector. Practical limitations concerning the generation of high-density interconnect arrays are described. Experimental results for 13 × 13, 21 × 21, and 50 × 50 spot arrays are presented.

Locality-based control algorithms for reconfigurable optical interconnection networks

Hybrid optoelectronic computing structures are required for providing the information processing capabilities for the next generation of computing and communications systems. Reconfigurable optoelectronic interconnection networks are networks constructed of optical waveguides in which messages are switched or routed by means of optoelectronic devices. For these networks, the dichotomy between the bandwidth of the optical channels that carry messages and the performance of the electronic controllers and decoders that determine the routing and destination of those messages is a significant bottleneck. We introduce a class of routing algorithms for reconfigurable networks that is designed to bridge this gap in optical versus electronic performance. The algorithms are based on a new control paradigm that exploits the locality in multiprocessor communication streams to reduce the control latency inherent in reconfigurable interconnection structures. In addition, we show that this problem maps directly to the problem of page replacement in a virtual-memory hierarchy. Thus our solution is well suited to networks for multiprocessor applications.

An expandable column fft architecture using circuit switching networks

The Fast Fourier Transform (FFT) is widely used in various digital signal processing applications. The performance requirements for FFT in modern real-time applications has increased dramatically due to the high demand on capacity and performance of modern telecommunication systems, where FFT plays a major role. Software implementations of FFT running on a general purpose computer can no longer meet current speed requirements. However, recent advances in VLSI technology have made it possible to implement the entire FFT system on a single silicon substrate. This article presents a column FFT design suitable for ULSI (Ultra Large Scale Integration) implementations. The basic building block is a 64-point column FFT. FFTs with longer transform lengths can be easily realized using the 64-point column FFT building block. The butterfly processors in the column FFT are connected using circuit switching networks. The circuit switching networks not only provide dynamically recon-figurable interconnections among the butterfly processors, but also provide a fault-tolerant capability. Bit-serial arithmetic is used in the architecture. Assuming the data word length is 16 bits, the 1024-point column FFT engine proposed in this article is capable of processing 1024 complex data samples in 533 clock cycles. If the clock frequency is 40 MHz, it will take 13.3 µs to complete a 1024-point FFT.