Reconfigurable FPGA Research Articles

FPGA-Based Dynamically Reconfigurable SQL Query Processing

In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row- as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.

Initial experiments of a 128-channel FPGA and PC-based ultrasound imaging system for teaching and research activities.

Although widely employed in medical diagnostic applications, most of the available commercial ultrasound (US) scanners do not always fit the needs of research users. Access to raw US data, portability, flexibility and advanced user control are essential features to explore alternative biomedical signal and imaging processing algorithms. In this paper, we present the initial results of a reconfigurable, cost-effective and modular 128-channel FPGA and PC-based US system, specifically designed for teaching and medical imaging research. The proposed system exploits the advantages of the MD2131 (Microchip Technology Inc.) beamformer source driver to generate arbitrary waveforms and the analog front-end AFE5805 (Texas Instruments Inc.) to obtain the maximum flexibility and wide data access to the various US data streams. Two applications involving plane wave excitation and delay-and-sum (DAS) beamforming are discussed. The results show that the open platform can help biomedical students and researchers to develop and evaluate different imaging strategies for medical US imaging and nondestructive testing (NDT) techniques, among other applications.

Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework

Partial dynamic reconfiguration of FPGAs gives designers the capability to change certain parts of the hardware while other parts remain active and in use. This provides several benefits including reducing device count and power consumption. However, this also introduces new challenges that need to be addressed by designers. This paper introduces a framework for efficient mapping of execution units to task graphs in a runtime reconfigurable system. The framework utilizes an Island Based Genetic Algorithm flow that optimizes several objectives including delay and power consumption. The GA based technique not only optimizes the above objectives, but also aggregates the Pareto front of the different islands to further enhance solution quality. The Island based GA runs each GA in parallel, and is amenable to both software and hardware implementation. The proposed Island based GA framework achieves on average 55.2% improvement over a single GA implementation and 80.7% improvement over a baseline random allocation and binding approach.

Hybrid two-stage HW/SW partitioning algorithm for dynamic partial reconfigurable FPGAs

Hybrid two-stage HW/SW partitioning algorithm for dynamic partial reconfigurable FPGAs

Tasks Scaling with Chameleon© C2HDL Design Tool in Self-Configurable Computer Systems Based on Partially Reconfigurable FPGAs

Tasks Scaling with Chameleon© C2HDL Design Tool in Self-Configurable Computer Systems Based on Partially Reconfigurable FPGAs

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.

Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs

The dynamic partial reconfiguration functionality of FPGAs can be attacked, particularly when the FPGA is remotely located or the configuration bitstreams are sent through insecure networks. The existing FPGA technologies provide some built-in security mechanisms; however, these are often inadequate. The existing solutions still impose a significant impact on the reconfiguration process and on the available resources. This article proposes a solution to improve the security of dynamic partial reconfiguration of FPGAs, without significantly affecting the reconfiguration performance. The proposed solution changes the encryption key of the remotely received bitstream by a randomly generated key, unique for each configuration, when storing them in the external unsecured memory. The native frame-wise error detection mechanism combined with an additional CBC-MAC authentication mechanism, allows for an improved countermeasure against replay attack and wrongful bitstream usage. The proposed solution introduces an overhead of 1% of the available resources on the target FPGA and provides the lowest impact on the reconfiguration process when compared to the state of the art, achieving a reconfiguration throughput of 2.5Gbps. Regarding the built-in security mechanism provided by the Xilinx FPGAs, the solution herein proposed provides better security and improves the reconfiguration performance by more than 3 times.

Design and Analysis of RTOs based Reconfigurable Cots Design on FPGA

Background:Due to greater potentialto accelerate a wide variety of application, reconfigurable FPGA has become a subject to great deal of research. The FPGA has ability to perform computations in hardware to increase the system performance, while retaining much of the flexibility of software solutions. In recent development, the real-time embedded system are increasingly being built with COTS components namely mass-produced peripherals and by reducing cost through buses and performance improvement. But the available COTS systems do not guarantee any timeliness and do not implement any priority scheduling mechanism. Methods/Statistical Analysis: This article deals with a new approach to create an RTOS based reconfigurable COTS design for FPGA platform. Thereby RTOS kernel is designed for FPGA and COTS system designed on the FPGA. Application/Improvements: At runtime, the hardware tasks are scheduled and allocated system resources like I/O, memory, etc. to successfully export multiple virtual devices for a single physical device. Keywords: FPGA, RTOS based Reconfigurable Commercial-off-the-Shelf

A new method of fault tolerance based on partial reconfiguration

When field programmable gate array FPGA applied in the space, it is easily subjected to the single event upset SEU effect which will cause the system breaking down. This paper introduces the principle of dynamic reconfiguration of FPGA, and puts forward a new design method based on embedded system with traditional fault-tolerant methods being analysed. It combines the triple modular redundancy TMR technique and the FPGA dynamic partial reconfiguration technique, to make the system complete self-detecting and self-healing. The design has been validated and analysed through simulation and testing, and the results turns to indicate that the new design method has strong ability of fault tolerance as well as highly credibility compared with traditional TMR technique.

An FPGA 2D-convolution unit based on the CAPH language

Convolution is an important operation in image processing applications, such as edge detection, sharpening and adding blurring. Convolving video streams in real time is a challenging task for PC systems, however, FPGA devices can successfully be used in these tasks. In this article, the design and implementation of a reconfigurable FPGA architecture for 2D-convolution filtering is described. The filtered frames are calculated at a rate of 103 frames per second for images up to $$1200\times 720$$ pixel resolution. Using a shift-based arithmetic and circular buffers, the developed FPGA architecture allows to reduce the hardware resource consumption up to 98 % compared to the conventional convolution implementations, provides high speed processing and enables to manage large number of different convolution kernels. On the other hand, using the CAPH language, it is possible to reduce the design time up to 75 % compared to the plain VHDL design. Furthermore, to maintain high flexibility in concordance with the input video, the developed hardware allows to configure the resolution of the input images with values of $$3\times \textit{Y}$$ up to $$1200\times \textit{Y}$$ , and allows scalability for different sizes of convolution kernels of simple and systematic form. Finally, the developed FPGA architecture for the proposed method was implemented and validated in an FPGA Cyclone II EP2C35F672C6 embedded in an Altera development board DE2.

Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies

This paper presents a multicore and multichannel (MCMC) technology and a synchronous and forward-backward scheduling (SFBS) for the cost reduction of sequential minimal optimization trainable pattern classifier. The MCMC technology uses multiple processing cores that are self-reconfigurable and preconfigurable. For different functions, five self-configurable modes and four preconfigurable modes can be combined to achieve high flexibility. A multichannel hierarchical architecture enables different transfer rates. To minimize communication cost, the SFBS uses synchronous and forward-backward counting for data scheduling. For implementation in reconfigurable FPGAs, MCMC and SFBS are combined for use in synthesis, placement, and routing. Compared with the baseline design, the emulation results show that the proposed architecture has a low area and low power costs (5755 logic elements and 195 mW), respectively. The experimental results confirm the cost improvement achieved by the proposed architecture and methods.

Design and Implementation of RSA Algorithm using FPGA

RSA cryptographic algorithm used to encrypt and decrypt the messages to send it over the secure transmission channel like internet. The RSA algorithm is a secure, high quality, public key algorithm. In this paper, a new architecture and modeling has been proposed for RSA public key algorithm, the suggested system uses 1024-bit RSA encryption/decryption for restricted system. The system uses the multiply and square algorithm to perform modular operation. The design has been described by VHDL and simulated by using Xilinx ISE 12.2 tool. The architectures have been implemented on reconfigurable platforms FPGAs. Accomplishment when implemented on Xilinx_Spartan3 (device XC3S50, package PG208, speed -4) which confirms that the proposed architectures have minimum hardware resource, where only 29% of the chip resources are used for RSA algorithm design with realizable operating clock frequency of 68.573 MHz.

The Long-distance Reconfiguration Design of FPGA Based on ARM

The task of this design is using the developing embedded technique, ARM to configurate FPGA, so that the re- configuration of FPGA can without dedicated configuration software, and the configuration of FPGA can no longer to connect with a computer. Save the configuration file in the memory chip, connect the ARM system to the Internet and re- mote access service to download configuration file for the configuration of FPGA. In the later period of this design, proc- ess the FPGA contiguration file(format conversion, encrypt, decode, etc.), and popularize this method to different series of FPGA. So that, the reconfiguration of FPGA do not need to connect FPGA with a computer, only need to get the configu- ration file. In this paper, structure NFS file system of ARM and computer is succeed, so does the wired communication and the process of configuration file, and the SP1 communication between ARM and FPGA for configuration is achieved.

ON CONVERGENCE OF GENETIC ALGORITHM FOR FPGA RECONFIGURATION

The article discusses the problem of increasing the reliability and fault tolerance of programmable logic integrated circuits of type FPGA. Currently there are several approaches to improve the reliability. One of them is to use elements with redundant basis, an appropriate diagnosis and reconfiguration. The aim of the study is to develop a genetic algorithm for FPGA reconfiguration, with the use of elements with redundant basis. Reconfiguration task is understood as a problem of finding a workable elements that cover a given functional circuit. These elements should be arranged more compactly. In this paper we prove a theorem, which theoretically justifies the convergence of the algorithm to an optimal solution. Practical experiments confirm the theoretical conclusions. The results can be used to develop new genetic algorithms and creating FPGA based on elements with redundant basis.

Definition of an Architecture to Configure Artificial Neural Networks Topologies Using Partial Reconfiguraton in FPGA

Artificial Neural Networks (ANNs) competence in generalization and reconfigurable hardware using provide a solid base to developing critical embedded systems, capable of efficiently adapt itself as requirements change. Different level adaptation, from physical level up to system level, can be combined to provide efficient solutions using FPGA. So, this work aims to define a novel architecture to configure ANNs topologies using partial FPGA reconfiguration. NEURON block has been described using fixed-point notation and applying partial reconfiguration to load partial bitstreams of sigmoid and hiperbolic tangent functions, as well as dynamically inserting and removing NEURON blocks on the net, this way it is possible to configure MultiLayer Perceptron (MLP) networks with different topologies, using partial bitstreams in reconfigurable areas. It is conceived that, using this kind of hardware facilitates embedding applications using different topologies, MLP ANNs, easily reconfigurable on the field.

An Efficient Algorithm for On-line Placement of Partially Reconfigurable Devices

Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA, which is useful for online placement and scheduling of HW tasks. The algorithm is incremental and only updates the local region affected by each task addition or removal event. Second, we present an efficient online deadline-constrained task placement algorithm for minimizing area fragmentation on the FPGA by using an area fragmentation metric that takes into account probability distribution of sizes of future task arrivals as well as the time axis. The techniques presented in this paper are useful in an operating system for runtime reconfigurable FPGAs to manage the HW resources on the FPGA when HW tasks that arrive and finish dynamically at runtime. Online placement methods are required that achieve a high placement quality and lead to efficient implementation.

Modules placement technique under constraint of FPGA forbidden zones

Runtime partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. Partial reconfigurable FPGAs allow tasks to be placed and removed dynamically at runtime. One of the challenging problems is the placement of modules on reconfigurable resources, this problem is called modules placement. Several modules placement techniques have been introduced in the literature to solve the modules placement problem. However, many designers have not considered forbidden zones inside the FPGA when loading the design. These forbidden zones inside FPGA might be the PowerPC, the Bloc RAMs, a design constraint, etc. Neglecting these FPGA forbidden zones may lead to incorrect design. In this paper, we present a new design method; the proposed method might be used early during the design process. It can help the designer to avoid FPGA forbidden zones when loading the design. Our method uses a typical mathematical formalism to load design on the device while avoiding the forbidden zones inside the FPGA and satisfying constraints at the same time. Experience shows that design results might be modified considerably when designer takes in account the FPGA forbidden zones.

Integrating reconfigurable hardware-based grid for high performance computing.

FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems

This article presents an approach for mapping real-time applications based on particle filters (PFs) to heterogeneous reconfigurable systems, which typically consist of multiple FPGAs and CPUs. A method is proposed to adapt the number of particles dynamically and to utilise runtime reconfigurability of FPGAs for reduced power and energy consumption. A data compression scheme is employed to reduce communication overhead between FPGAs and CPUs. A mobile robot localisation and tracking application is developed to illustrate our approach. Experimental results show that the proposed adaptive PF can reduce up to 99% of computation time. Using runtime reconfiguration, we achieve a 25% to 34% reduction in idle power. A 1U system with four FPGAs is up to 169 times faster than a single-core CPU and 41 times faster than a 1U CPU server with 12 cores. It is also estimated to be 3 times faster than a system with four GPUs.

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming.FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis.