Modules placement technique under constraint of FPGA forbidden zones

Abstract

Runtime partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. Partial reconfigurable FPGAs allow tasks to be placed and removed dynamically at runtime. One of the challenging problems is the placement of modules on reconfigurable resources, this problem is called modules placement. Several modules placement techniques have been introduced in the literature to solve the modules placement problem. However, many designers have not considered forbidden zones inside the FPGA when loading the design. These forbidden zones inside FPGA might be the PowerPC, the Bloc RAMs, a design constraint, etc. Neglecting these FPGA forbidden zones may lead to incorrect design. In this paper, we present a new design method; the proposed method might be used early during the design process. It can help the designer to avoid FPGA forbidden zones when loading the design. Our method uses a typical mathematical formalism to load design on the device while avoiding the forbidden zones inside the FPGA and satisfying constraints at the same time. Experience shows that design results might be modified considerably when designer takes in account the FPGA forbidden zones.