Reconfigurable Field Programmable Gate Array Research Articles

Solar powered high gain DC-DC converter with FPGA controller for portable devices

A solar-powered converter design is necessary for portable devices with increased gain and reduced ripple in overall operation. This research presents a photovoltaic-powered Field Programmable Gate Array (FPGA) based on increased gain multiple output converter design and analysis. The dynamic panel input makes it difficult to operate the load. To control and make the input static to satisfy the demand, perturb and observe with a load balancing algorithm technique are used. The converter gained output is high, and batteries are used to balance the loads when solar irradiance is low. Simulation results were carried out with the presented converter circuit that can be operated with a 12 V supply as input from a renewable power source. The output gain ratio of 14 to a minimum of 40 % duty cycle operating at a switching frequency of 20 kHz has been achieved. The proposed methodology is transferred to hardware by connecting with the reconfigurable FPGA Spartan-6 development board to manage the dynamic load control system's complex logic and high processing ability. The overall performance is compared with various pre-existing systems, tabulations are made with the analysis, and experimental results are also illustrated at the end.

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

Many high-demand digital services need to perform several cryptographic operations, such as key exchange or security credentialing, in a concise amount of time. In turn, the security of some of these cryptographic schemes is threatened by advances in quantum computing, as quantum computer could break their security in the near future. Post-Quantum Cryptography (PQC) is an emerging field that studies cryptographic algorithms that resist such attacks. The National Institute of Standards and Technology (NIST) has selected the CRYSTALS-Kyber Key Encapsulation Mechanism and the CRYSTALSDilithium Digital Signature algorithm as primary PQC standards. In this paper, we present FPGA-based hardware accelerators for high-volume operations of both schemes. We apply High-Level Synthesis (HLS) for hardware optimization, leveraging a batch processing approach to maximize the memory throughput, and applying custom HLS logic to specific algorithmic components. Using reconfigurable field-programmable gate arrays (FPGAs), we show that our hardware accelerators achieve speedups between 3x and 9x over software baseline implementations, even over ones leveraging CPU vector architectures. Furthermore, the methods used in this study can also be extended to the new CRYSTALS-based NIST FIPS drafts, ML-KEM and ML-DSA, with similar acceleration results.

Design of a New Neuro-Generator with a Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences

This paper presents the design of a new neuro-generator of pseudorandom number type PRNG Pseudorandom Number Generator, which produces complex sequences with an adequate bit distribution. The circuit is connected to a neuronal module with six impulse neurons with different behaviors: spike frequency adaptation, phasic spiking, mixed mode, phasic bursting, tonic bursting and tonic spiking. This module aims to generate a non-periodic signal that becomes the clock signal for one of the LFSRs Linear Feedback Shift Register that the neuro-generator has. To verify its correct operation, the neuro-generator was subjected to a series of tests where the frequencies of the impulse neurons were modified. This modification allows the generation of a greater number of pulses at the output of the neuronal module, to obtain sequences with different characteristics that pass different NIST statistical tests (National Institute of Standards and Technology of U.S.). The results show that the new neuro-generator maintains pseudo-randomness in the sequences obtained with different frequencies and it can be implemented on a reconfigurable FPGA Field Programmable Gate Array Virtex 7 xc7vx485t-2ffg1761 device. Therefore, it can be used for applications such as biological systems.

Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.

The development of prostheses and treatments for illnesses and recovery has recently been centered on hardware modeling for various delicate biological components, including the nervous system, brain, eyes, and heart. The retina, being the thinnest and deepest layer of the eye, is of particular interest. In this study, we employ the Nyquist-Based Approximation of Retina Rod Cell (NBAoRRC) approach, which has been adapted to utilize Look-Up Tables (LUTs) rather than original functions, to implement rod cells in the retina using cost-effective hardware. In modern mathematical models, numerous nonlinear functions are used to represent the activity of these cells. However, these nonlinear functions would require a substantial amount of hardware for direct implementation and may not meet the required speed constraints. The proposed method eliminates the need for multiplication functions and utilizes a fast, cost-effective rod cell device. Simulation results demonstrate the extent to which the proposed model aligns with the behavior of the primary rod cell model, particularly in terms of dynamic behavior. Based on the results of hardware implementation using the Field-Programmable Gate Arrays (FPGA) board Virtex-5, the proposed model is shown to be reliable, consume 30 percent less power than the primary model, and have reduced hardware resource requirements. Based on the results of hardware implementation using the reconfigurable FPGA board Virtex-5, the proposed model is reliable, uses 30% less power consumption than the primary model in the worth state of the set of approximation method, and has a reduced hardware resource requirement. In fact, using the proposed model, this reduction in the power consumption can be achieved. Finally, in this article, by using the LUT which is systematically sampled (Nyquist rate), we were able to remove all costly operators in terms of hardware (digital) realization and achieve very good results in the field of digital implementation in two scales of network and single neuron.

Development of embedded fuzzy control using reconfigurable FPGA technology

The purpose of this work is to investigate the construction of fuzzy embedded control systems combining fast execution and parallel processing capabilities provided by Field Programmable Gate Arrays (FPGAs) and Reconfigurable Inputs/Outputs (RIO) chips. A fixed-point fuzzy controller is developed and implemented on a fast mechatronic system with high-speed control and high channel count on an FPGA target. This paper provides a brief introduction to deploying Fuzzy Logic Control (FLC) methods using RIO-FPGA technology. It suggests a technique for implementing the three stages that constitute the FLC and the PD-like FLC and PID-like FLC structures into practice. Controllers with 1 and 2 degrees of freedom are developed and tested experimentally. Parallel loops, key challenging advantage of LabVIEW programming, are utilized for decoding feedback signals, generating pulse trains for actuator's drivers and for calculation of control gains. An NI-SbRIO board that combines deployable devices with a real-time processor, a re-configurable FPGA, and analogue and digital input–output ports is used. The experimental work demonstrates the significant enhancement of implementing reconfigurable embedded fuzzy control upon such mechatronic systems.

Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces

Reconfigurable intelligent surfaces (RIS) offer the potential to customize the radio propagation environment for wireless networks, and will be a key element for 6G communications. However, due to the unique constraints in these systems, the optimization problems associated to RIS configuration are challenging to solve. This paper illustrates a new approach to the RIS configuration problem, based on the use of artificial intelligence (AI) and deep learning (DL) algorithms. Concretely, a custom convolutional neural network (CNN) intended for edge computing is presented, and implementations on different representative edge devices are compared, including the use of commercial AI-oriented devices and a field-programmable gate array (FPGA) platform. This FPGA option provides the best performance, with ×20 performance increase over the closest FP32, GPU-accelerated option, and almost ×3 performance advantage when compared with the INT8-quantized, TPU-accelerated implementation. More noticeably, this is achieved even when high-level synthesis (HLS) tools are used and no custom accelerators are developed. At the same time, the inherent reconfigurability of FPGAs opens a new field for their use as enabler hardware in RIS applications.

FPGA Implementation for Finite-Time and Fixed-Time Neurodynamic Algorithms in Constrained Optimization Problems

In this paper, two neurodynamic algorithms and the corresponding Field-Programmable-Gate-Array (FPGA) implementation scheme are presented, respectively. Firstly, based on Lagrange programming neural networks (LPNN) and sliding mode control technique, an algorithm with finite-time convergence and an algorithm with fixed-time convergence is proposed and used to solve constrained optimization problems. Then, the Update module, the Control module, the Gradient module, the finite-time processing (FTP) module, and the fixed-time processing (FxTP) module are designed to form an FPGA hardware implementation of neurodynamic optimization algorithms. The LPNN-based FPGA reconfigurable circuit framework can be structured by invoking the Update module, the Control module, and the Gradient module. The FTP module or the FxTP module can be called into the above framework to form the finite-time or fixed-time stable FPGA reconfiguration framework. Finally, the effectiveness and practicality of the proposed FPGA hardware implementation scheme is verified through example simulations implemented on the Vivado 2019.1 platform.

Throughput/Area-Efficient Accelerator of Elliptic Curve Point Multiplication over GF(2233) on FPGA

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over GF(2233). The throughput of the proposed accelerator design is optimized by reducing the total clock cycles using a bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize the hardware resources: (i) a consolidated arithmetic unit where we combine a single modular adder, multiplier, and square block instead of having multiple modular operators, and (ii) an Itoh–Tsujii inversion algorithm by leveraging the existing hardware resources of the multiplier and square units for multiplicative inverse computation. An efficient finite-state-machine (FSM) controller is implemented to facilitate control functionalities. To evaluate and compare the results of the proposed accelerator architecture against state-of-the-art solutions, a figure-of-merit (FoM) metric in terms of throughput/area is defined. The implementation results after post-place-and-route simulation are reported for reconfigurable field-programmable gate array (FPGA) devices. Particular to Virtex-7 FPGA, the accelerator utilizes 3584 slices, needs 7208 clock cycles, operates on a maximum frequency of 350 MHz, computes one ECPM operation in 20.59 μs, and the calculated value of FoM is 13.54. Consequently, the results and comparisons reveal that our accelerator suits applications that demand throughput and area-optimized ECPM implementations.

Automated design and usage of the Fault-Tolerant dynamic partial reconfiguration controller for FPGAs

This article presents a new design automation method for Fault-Tolerant (FT) systems implemented on dynamically reconfigurable Field Programmable Gate Arrays (FPGAs). The method aims at minimizing the human interactions needed to incorporate FT mechanisms into an existing system. It starts with a source code of an original unhardened circuit. It continues by automated manipulation of the source code, algorithmic strategic selection of suitable FT techniques, design space exploration of candidate FT implementations, and selection of the resulting implementation. The method also includes efficient evaluation of achieved FT parameters performed on the target HW. As a novel approach working on the level of HW description languages is employed, the code modification is separated, which differentiates our method from others. The case study utilizing this method targets the design of an experimental FT dynamic partial reconfiguration controller for an FPGA. This controller is helpful for the restoration of faulty components due to a single-event upset on an FPGA. We used the method to generate a set of Pareto-optimal controllers concerning the design’s Mean Time to Failure (MTTF) parameter, power consumption, and size. Then, the FT controller is connected to several benchmark circuits, and the reliability parameters are evaluated at the entire system level. Our results show that by replacing the standard reconfigurable controller with our automatically-designed FT controller for one specific benchmark, the design size increased by 20.1%, and MTTF increased by 11.7%. However, the efficiency is highly dependent on the target system size, MTTF, and circuit functionality. We also estimate that a complex system defined by half a million configuration bits would improve MTTF by more than 50%.

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis

Field programmable gate arrays (FPGAs) have become widely prevalent in recent years as a great alternative to application-specific integrated circuits (ASIC) and as a potentially cheap alternative to expensive graphics processing units (GPUs). Introduced as a prototyping solution for ASIC, FPGAs are now widely popular in applications such as artificial intelligence (AI) and machine learning (ML) models that require processing data rapidly. As a relatively low-cost option to GPUs, FPGAs have the advantage of being reprogrammed to be used in almost any data-driven application. In this work, we propose an easily scalable and cost-effective cluster-based co-processing system using FPGAs for ML and AI applications that is easily reconfigured to the requirements of each user application. The aim is to introduce a clustering system of FPGA boards to improve the efficiency of the training component of machine learning algorithms. Our proposed configuration provides an opportunity to utilise relatively inexpensive FPGA development boards to produce a cluster without expert knowledge in VHDL, Verilog, or the system designs related to FPGA development. Consisting of two parts – a computer-based host application to control the cluster and an FPGA cluster connected through a high-speed Ethernet switch, allows the users to customise and adapt the system without much effort. The methods proposed in this paper provide the ability to utilise any FPGA board with an Ethernet port to be used as a part of the cluster and unboundedly scaled. To demonstrate the effectiveness of the proposed work, a two-part experiment to demonstrate the flexibility and portability of the proposed work – a homogeneous and heterogeneous cluster, was conducted with results compared against a desktop computer and combinations of FPGAs in two clusters. Data sets ranging from 60,000 to 14 million, including stroke prediction and covid-19, were used in conducting the experiments. Results suggest that the proposed system in this work performs close to 70% faster than a traditional computer with similar accuracy rates.

Accurate and efficient molecular dynamics based on machine learning and non von Neumann architecture

Force field-based classical molecular dynamics (CMD) is efficient but its potential energy surface (PES) prediction error can be very large. Density functional theory (DFT)-based ab-initio molecular dynamics (AIMD) is accurate but computational cost limits its applications to small systems. Here, we propose a molecular dynamics (MD) methodology which can simultaneously achieve both AIMD-level high accuracy and CMD-level high efficiency. The high accuracy is achieved by exploiting deep neural network (DNN)’s arbitrarily-high precision to fit PES. The high efficiency is achieved by deploying multiplication-less DNN on a carefully-optimized special-purpose non von Neumann (NvN) computer to mitigate the performance-limiting data shuttling (i.e., ‘memory wall bottleneck’). By testing on different molecules and bulk systems, we show that the proposed MD methodology is generally-applicable to various MD tasks. The proposed MD methodology has been deployed on an in-house computing server based on reconfigurable field programmable gate array (FPGA), which is freely available at http://nvnmd.picp.vip.

Denoising electrocardiogram signals using multiband filter and its implementation on FPGA

The electrocardiogram (ECG) signal carries vital information related to cardiac activities. While measuring ECG using electrodes, the signal is contaminated with powerline interference (PLI) from harmonics, baseline wandering (BW), motion artefacts (MA) and high frequency (HF) noise. The extraction of the ECG signal, without the loss of useful information from the noisy environment, is required. Therefore, the selection and implementation of an efficient filter design is proposed. The Finite Impulse Response (FIR)-based multiband needs separate digital filters, such as Lowpass, Highpass, and Bandstop Filter in cascade. The coefficients of the FIR multiband filter are optimised using a least squares optimisation method and realised in a direct form symmetrical structure. The capability of the proposed filter is evaluated on a Physionet ECG ID database, having records of inherent noisy ECG signals. The performance is also verified by measuring the power spectrum of the noisy and filtered ECG waveform. Also, the feasibility of the proposed multiband filter is investigated on Xilinx ISE and the design is implemented on a field programmable gate array (FPGA) platform. A low order simple multiband filter structure is designed and implemented on the reconfigurable FPGA device.

A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net

A reconfigurable field-programmable gate array (FPGA)-based wired-logic deep neural network (DNN) accelerator is presented. High energy efficiency of 16 nJ/classification (Modified National Institute of Standards and Technology: MNIST) is achieved due to the wired-logic architecture. Each neuron in the neural network consists of combinational circuits only, and all the neurons are implemented on an FPGA. Intermediate data are never stored in memory or registers and are transmitted to the output stage by passing through only neuron cells. The latency and power required for memory access can be minimized, enabling low power and high throughput operation. A critical technical issue is reducing hardware resources because all neurons need to be implemented on an FPGA, where hardware resources are limited. Two core technologies have been developed to minimize the required hardware resources: (1) A neural network with a small number of neurons in which weight values of all synapses are fixed to a common value, and (2) a small neuron cell circuit consisting of an adder and look-up table containing an activation function. By fixing all weight values to a certain common value, processing can be simplified from multiply-accumulate operations to just additions, and the hardware resources required for each neuron are minimized. An experiment with the MNIST dataset using a 28-nm FPGA confirmed power consumption of 0.16 W and latency per inference of 100 ns (16nJ/classification). With the same recognition accuracy, the power efficiency is 45.6 times higher than that of the conventional state-of-the-art binarized DNN accelerator with a digital ASIC.

Epileptic Seizure Recognition Using Reduced Deep Convolutional Stack Autoencoder and Improved Kernel RVFLN From EEG Signals.

In this paper, reduced deep convolutional stack autoencoder (RDCSAE) and improved kernel random vector functional link network (IKRVFLN) are combined to recognize the epileptic seizure using both the multichannel scalp and single-channel electroencephalogram (EEG) signals. The novel RDCSAE structure is designed to extract the most discriminative unsupervised features from EEG signals and fed into the proposed supervised IKRVFLN classifier to train efficiently by reducing the mean-square error cost function for recognizing the epileptic seizure activity with promising accuracy. The proposed RDCSAE-IKRVFLN algorithm is tested over the benchmark Boston Children's Hospital multichannel scalp EEG (sEEG) and Boon University, Germany single-channel EEG databases. The less computational complexity, higher learning speed, better model generalization, accurate epileptic seizure recognition, remarkable classification accuracy, negligible false positive rate per hour (FPR/h) and short event recognition time are the main advantages of the proposed RDCSAE-IKRVFLN method over reduced deep convolutional neural network (RDCNN), RDCSAE and RDCSAE-KRVFLN methods. The proposed RDCSAE-IKRVFLN method is implemented in a high-speed reconfigurable field-programmable gate array (FPGA) hardware environment to design a computer-aided-diagnosis (CAD) system for automatic epileptic seizure diagnosis. The simplicity, feasibility, and practicability of the proposed method validate the stable and reliable performances of epilepsy detection and recognition.

A CORDIC based real-time implementation and analysis of a respiratory central pattern generator

Central pattern generators (CPGs) are dedicated neural circuits which can generate rhythmic motor patterns even in absence of sensory input with extraordinary robustness and flexibility. In this paper, a biologically realistic model of a respiratory CPG with four neurons is implemented on a reconfigurable Field-Programmable Gate Array (FPGA) system. Considering the limitations of hardware resources, we first propose a modified respiratory CPG model with Coordinate Rotation Digital Computer (CORDIC) algorithm to save limited resources and reduce complexity. And then, all the multipliers are replaced with a method which is appropriate and effective for hardware implementation to avoid the use of the area-intensive multipliers. The implementation results show that rhythmic oscillations are successfully generated by the respiratory CPG network and the resource utilization is greatly reduced, which shows the potential for building large-scale spiking neural networks. The proposed high-performance and real-time implementation of the respiratory CPG network on the FPGA system can speed up the process to gain new insights into the respiratory network and can also be developed into applications for respiratory rhythm generation and modulation.

Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs

Field programmable gate array (FPGA) is ubiquitous nowadays and is applied to many areas. Dynamic partial reconfiguration (DPR) is introduced to most modern FPGAs, enabling changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. However, delivering the powerful capacity of the DPR FPGA to the user depends on the efficient partitioning and scheduling technology. This article proposes the module merging technique for the partitioning and scheduling problem to reduce the reconfiguration overhead and improve the schedule performance. An exact approach based on the integer linear programming (ILP) for the partitioning and scheduling problem with module merging is proposed. The ILP-based approach is capable of solving the problem optimally, and can be used to further improve the performance of schedules produced by other non-optimal algorithms; however, it is time-consuming to solve large-scale problems. Therefore, a K-sliced-ILP algorithm based on the methodology of divide-and-conquer is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. Experiments are carried out with a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

This paper examines the feasibility of using commercial out-of-the-box Reconfigurable Field Programmable Gate Array (FPGA) technology and the OpenCL framework to create efficient Sobel edge-detection implementation, which is considered a fundamental part in the field of image and video processing. The revised proposed approach was created at a high level of abstraction and executed on high commodity Intel FPGA platform. This was performed in a manner that was designed to allow the high-level compiler/synthesis tool to manipulate a task a parallelism model. The most promising FPGA and the naive implementations were compared to their single-core CPU software equivalents while manipulating local-memory, pipelining, loop unrolling, vectorization, internal channels mechanisms and memory coalescing to provide a much more effective hardware design. The run-time and the power consumption attributes were estimated for each implementation. The proposed FPGA based implementations were found to have significantly better runtime and power consumption with approximately up to 37 folds of improvement in the whole execution/transfer time, and up to 53 folds of improvement in energy consumption when compared to a specific single-core CPU based implementation.

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on static random-access memory (SRAM)-based partially run-time reconfigurable field programmable gate arrays (FPGAs) in harsh environments by taking both single-bit upsets and multiple-cell upsets into account. The model requires some features of the hardware tasks, including their computation time, size, the percent of critical bits, and the soft error rates of k-bit events (k ≥ 1) of the environment for the reliability estimation. Such an early estimation helps the developers to assess the reliability of their designs at earlier stages and leads to reduce the development cost. The proposed model has been evaluated by conducting several experiments on actual hardware tasks over different environmental soft error rates. The obtained results, endorsed by the 95% confidence interval, reveal the high accuracy of the proposed model. When comparing this approach with a reliability model (developed by the authors in a previous work) that does not consider the occurrence of multiple-cell upsets, an overestimation of the mean time to failure of 2.88X is observable in the latter. This points to the importance of taking into account multiple events, especially in modern technologies where the miniaturization is high.

Improved Fuzzy Logic Controller Implemented on FPGA Circuit for Photovoltaic Systems

To be the photovoltaic arrays capable to transport the maximum power obtainable, it must be combined with Maximum Power Point Tracking (MPPT). To succeed, we will improve a Maximum Power Point Tracking (MPPT) method, based on intelligent technique such as Fuzzy Logic Controller (FLC), compared with a conventional method which is P&O. This improved method applied to a stand-alone photovoltaic system under loading conditions and atmospheric data (temperature and irradiance). The goal of this controller is to prove that the FLC is the best technique of MPPT to extract the maximum power of photovoltaic modules. The main objective of this work is the implementation on a “Cyclone II” circuit using “EP2C35F672C6” Development Board reconfigurable Field-Programmable Gate Array (FPGA) with Hardware Description Language (VHDL). Thus, we show the advantages of using the FPGA circuits, which are their short progress time, their low price and their suppleness of process. The close optimum design of this technique is based on the best choice membership functions and control rules for two- input, one-output digital Fuzzy Logic Controller (FLC) based on “Mamdani” mechanism. The simulation and implementation results obtained respectively with waveform under Quartus software and on Cyclone II, both show a satisfactory performance and confirm the good tracking efficacy and speedy response to various atmospheric conditions.

AWARE-CNN: Automated Workflow for Application-Aware Real-Time Edge Acceleration of CNNs

This article presents the application-aware real-time edge acceleration of CNNs (AWARE-CNNs) accelerators, which is a novel architecture design methodology for real-time execution of deep learning algorithms on IoT devices. AWARE leverages the reconfigurability of field-programmable gate arrays (FPGAs) to create application-specific architectures customized to match the inherent dataflow of targeted deep neural networks and user-specified real-time requirements. The customized datapath is combined with a customized memory path to guarantee deterministic latency-aware execution over streaming data. For results and evaluation, we have developed a Chisel-based implementation of AWARE-CNN with a full integrative framework for application-specific architecture generation and synthesis (AWARE-CNN architecture compiler). Our results demonstrate the ability to execute Tiny DarkNet and shallow MobileNet inference at 120 frames/s (FPS) and 75 FPS, using only 2.8 and 3.4 W, respectively, on a Xilinx XCZU9EG FPGA. In addition, AWARE-CNN framework’s flexibility with respect to the targeted convolutional neural networks and user constraints is validated by targeting additional design points for AlexNet (as a baseline network) and Tiny YOLOv2.