Reconfigurable Fast Fourier Transform Research Articles

Reconfigurable Multi-Butterfly Parallel Radix-r FFT Processor

The design of reconfigurable multi-butterfly parallel radix-r FFT (Fast Fourier Transform) processors is proposed. FFT is widely used in signal processing, and the application needs real-time and high performance, while most of the traditional designs are limited to the power of two, which wastes the buffers and multipliers in big data. In response to the problem, we improve the parallel FFT algorithm with the design of reconfigurable control machine combined with buffer/multiplier, and the cost function with the input of radix/number/paddling number/time consuming is deduced. Constrained with the number of buffer and multipliers, the radix and number can be computed with the optimum cost function, and the resolution space of computing performance and hardware cost is presented. The proposed guarantees the real-time performance with better flexibility compared with the previous literature, and the comparison also suggests the effectiveness of the design.

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements

In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to 4096 FFT points, which are defined in current 3GPP-LTE communication system. The built-up design structure is primarily constructed on a radix-52 basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm2 and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation.

A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms

The fast Fourier transform (FFT) algorithm is widely used in digital signal processing systems (DSPs); hence, the development of a high-performance and resource-efficient FFT processor that conforms to the processing and precision requirements of real-time signal processing is highly desirable. We propose an FFT processor for field programmable gate array (FPGA) devices, based on the radix-2-decimation-in-frequency (R2DIF) algorithm. An appropriately modified parallel double-path delay commutator (DDC) architecture for radix-2 with continuous dual-input and dual-output streams (CoDIDOS) is proposed to increase throughput and reduce latency in FFT computation. The chip-area of the proposed design is reduced by decreasing the memory footprint of the complex twiddle factor multipliers. A multiplication scheme based on a combination of the unrolled coordinate rotation digital computer (CORDIC) and the canonical signed digit-based binary expression (CSDBE) is used to multiply the complex twiddle factors without requiring memory blocks for their storage. The CSDBE technique is proposed to optimize the multiplication of constants in the architecture. The proposed FFT processor is implemented as an intellectual property (IP) core and tested on a Xilinx Virtex-7 FPGA. Experimental results confirm that the proposed design improves the speed, latency, throughput, accuracy, and resource utilization of computation on FPGA devices over existing designs.

VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

Fast Fourier transform (FFT) plays an important role in digital signal processing systems. In this study, the authors explore the very large-scale integration (VLSI) design of high-precision fixed-point reconfigurable FFT processor. To achieve high accuracy under the limited wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. In addition, a statistics-based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the most optimised accuracy for a given FFT length. On the basis of this approach, they further present a VLSI implementation of area-efficient and high-precision FFT processor, which can perform power-of-two FFT from 32 to 8192 points. By using the SMIC 0.13 μ m process, the area of the proposed FFT processor is 27 m m 2 with a maximum operating frequency of 400 MHz. When the FFT processor is configured to perform 8192-point FFT at 40 MHz, the signal-to-quantisation-noise ratio is up to 53.28 dB and the power consumption measured by post-layout simulation is 35.7 mW.

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications

This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture, supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design concept is mainly based on combined radix-5, radix-32, and radix24 single-path delay feedback FFT design approaches. In addition, in order to elaborate our hardware design, we also develop three design techniques, such as reconfigurable processing kernel with seven types (RPK-ST), efficient FIFO management scheme, and single-table approximation method. In an ASIC implementation with TSMC 40-nm CMOS technology, our 46-mode reconfigurable FFT chip only occupies a core area of 0.36 mm2, dissipates 48.46 mW, and operates up to clock frequency of 500 MHz. As compared with the other state-of-the-art works, our work delivers high-quality design results in the aspects of area- and energy-related performance indexes, providing a constructive FFT design prototyping for 3GPP-LTE systems.

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems

Abstract This paper presents a reconfigurable Fast Fourier Transform (FFT) hardware architecture for 3GPP LTE systems. In the main FFT computing process, a novel processing kernel engine is proposed to support four configuration types of changeable hybrid-radix FFT operations. Also, in the data storage manipulation, a smart 2D-FIFO structure is used to flexibly handle efficient reading/writing data access for 36 different FFT sizes. In addition to a field-programmable gate array prototyping design approach, we provide application-specific integrated circuit implementation via TSMC 90-nm CMOS technology. The developed FFT chip only occupies a core area of 1 . 416 mm 2 , consumes 24.2 mW of power, and reaches maximum speed of 111.11 MHz.

A Flexible CO-OFDM Using Reconfigurable Multi-Precision FFT

To improve flexibility, energy efficiency, and speed of elastic optical orthogonal frequency division multiplexing systems, a reconfigurable multi-precision fast Fourier transform (FFT) is presented. The minimum required FFT word length for different criteria—namely, the bit error rate (BER), FFT size, modulation format, and optical signal-to-noise ratio—is determined using simulations. At run time, system performance is improved significantly by using a reconfigurable multi-precision FFT, while the target BER is satisfied. The proposed design is synthesized on an FPGA, and the results show that both energy efficiency and processing speed are improved about 79% and 78%, respectively, compared with the conventional design.

A low-area dynamic reconfigurable MDC FFT processor design

Fast Fourier Transform (FFT) is widely utilized to perform data computation in orthogonal frequency-division multiplexing (OFDM) systems. Wireless networks use 64-point to 512-point FFT to implement task. However, different FFT protocols have different lengths. Building all required points into circuits independently leads to a massive hardware resource requirement. To minimize the hardware resource requirement, Partial dynamic reconfiguration (PDR) FPGA can be adopted to build FFT modules and switched using time-independent circuits, which increasing the system design flexibility. The proposed FFT processor uses 64-point FFT on a static circuit, with other points configured as reconfigurable modules (RMs). The system can configure 64 to 512 points under different environment, and using PDR also reduced the occupied hardware resources. This work presents a four-path Multipath Delay Commutator (MDC), which can increase the FFT processor throughput. The twiddle factor (T.F.) computational circuits in FFT can be implemented with a right shift and adder circuits to calculate the fixed-point format to minimize the design complexity. Experimental results illustrate that the proposed design can increase the throughput of FFT processor, and reduce the number of FPGA slices by up to 76.6% at 256-point FFT, and the flip-flop by up to 58.9% at 64-point FFT.

Reconfigurable and Reusable Mutual Module Based Parameterization Approach for DWT and FFT Algorithm

Goal of this research article is to study and the analysis of a parameterization technique called Common Operator for an embedded digital signal processing system and implementation of that embedded system using a special architecture to achieve better performance. This can be realized by efficient hardware design with reduced area and low-power dissipation which is a significant challenge for embedded systems, particularly in portable devices. The challenge is even more pronounced when DWT and FFT with large transform lengths need to be realized in embedded hardware for several embedded signal processing applications. When it comes to miniaturization or reuse or sharing of the hardware, two Parameterization approaches, viz; the Common Function approach and the Common Operator approach are the effective ones. But in this study, it is proposed a reconfigurable FFT (Fast Fourier Transform) operator using the common operator approach. This operator can be reconfigured to switch from an operator dedicated to compute the FFT to an operator which computes the FFT in order to perform DWT. Contribution of this study is to Minimize the waste of resources by modifying slightly the FFT butterfly to support the DWT computation and to reduce the resources allocated to the reconfiguration, Simplify the reconfiguration between the two algorithms, by separating the calculation of the Real and Imaginary parts of FFT modules.

FPGA implementation of a re-configurable fft for multi-standard systems in software radio context

This study is focused on the Field Programmable Gate Array (FPGA) implementation of a re-configurable Fast Fourier Transform (FFT) operator able to provide Fourier transforms both over complex infinite field X and Galois finite Field GF. This new re-configurable FFT exploits to a great advantage the possibility to share hardware resources when considering multi-standard scenarios for software radio systems. A re-configurable FFT of length N = 256 has been implemented on FPGA. It achieves a performance-to-cost ratio gain from 24% to 9.4% compared to the basic duplicated solution for which no re-configuration is considered. The proposed technology is strongly connected to further consumer handheld devices such as mobile phones intended to support several standards (digital television, mobile communications, wireless local area network etc) where FFT is involved.

Low-Power-Adaptive MC-CDMA Receiver Architecture

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.