Reconfigurable Fabric Research Articles

An analysis of computational models for accelerating the subtractive pixel adjacency model computation

Detecting covert information in images by means of steganalysis techniques has become increasingly necessary due to the amount of data being transmitted mainly through the Internet. However, these techniques are computationally expensive and not much attention has been paid to reduce their cost by means of available parallel computational platforms. This article presents two computational models for the Subtractive Pixel Adjacency Model (SPAM) which has shown the best detection rates among several assessed steganalysis techniques. A hardware architecture tailored for reconfigurable fabrics is presented achieving high performance and fulfilling hard real-time constraints. On the other hand, a parallel computational model for the CUDA architecture is also proposed. This model presents high performance during the first stage but it faces a bottleneck during the second stage of the SPAM process. Both computational models are analyzed in detail in terms of their algorithmic structure and performance results. To the best of Authors’ knowledge these are the first design proposals to accelerate the SPAM model calculation.

Power and quality-aware image processing soft-resilience using online multi-objective GAs

A self-aware signal processing architecture is proposed based on adaptive resource escalation which is guided by a multi-objective genetic algorithm (GA). The GA prioritises tasks within a reconfigurable hardware fabric to maintain the quality-of-service and power consumption objectives. Attainment of these objectives is subject to the intrinsic reliability and performance of the computational elements in the resource pool. A health metric at the application layer, such as peak-signal-to-noise ratio (PSNR) measurement in a discrete cosine transform (DCT) or measure of confidence in a support vector machine (SVM) classifier, is used to assess throughput performance. When performance decreases beyond acceptable tolerances, the primary objective is to maximally recover output quality. The secondary objective is to minimise power consumption which also depends upon the input signal characteristics, in addition to the utilised computational resources. An adaptive guidance function for GA-driven recovery is proposed and validated for these objectives. It retains healthy processing elements in the throughput data path to gracefully-degrade throughput by optimising resource selection.

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. (C) 2014 Elsevier B.V. All rights reserved.

Reconfigurable Adder Architectures for Low Power Applications

The growing design complexity has attracted the designs with Reconfigurable fabrics, where adaptable fabrics are utilized to solve the computational problems. Reconfigurable computing provides the flexibility in arriving at the problem specific architectures which helps in improving the performance due to custom approach. In this paper, a flexible reconfigurable architecture with different adder variants like Ripple Carry, Carry Look-ahead, Carry Select and Carry Bypass adders are implemented to form dynamically reconfigurable Hybrid adder architectures. Such hybrid architectures are utilized for the applications where design constraints are only for low power or high performance or the low area or sometimes a balanced design metrics. The design was modelled using Verilog HDL and synthesized in Synopsys Design Compiler by mapping to TSMC 65nm technology node. Standard ASIC design methodologies are considered to bench mark the results. The proposed architecture enables the designer to perform efficient Design Space Exploration. The design can be made adaptable to any of the reconfigurable processor and a similar improvement can be obtained. The proposed architectures results in 18-54% reduced power consumption when designed with various combinations of reconfigurable adder architectures and also accounted for 14-44% of area reduction.

A reconfigurable fabric for accelerating large-scale datacenter services

Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6x8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server, accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb SAS cables In this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system when ranking candidate documents. Under high load, the largescale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution--- or, while maintaining equivalent throughput, reduces the tail latency by 29%

Scalable Open-Source Architecture for Real-Time Monitoring of Adaptive Wiring Panels

The first prototype of an adaptive wiring panel was recently introduced that implemented a reconfigurable switch fabric that allows dynamic routing of analog, digital, and power signals for space system applications. In this paper, a complete redesign and reimplementation of the adaptive wiring panel system is considered to address issues associated with scalability, reliability, and real-time monitoring of the switching fabric. The new system is demonstrated using 48 cells as opposed to the six cells of the first adaptive wiring panel prototype. The hardware and software systems are open source, and recommendations are provided to support further extensions to the system.

Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform

Emerging hybrid reconfigurable platforms tightly couple capable processors with high performance reconfigurable fabrics. This promises to move the focus of reconfigurable computing systems from sta...

Complex photonic lattices embedded with tailored intrinsic defects by a dynamically reconfigurable single step interferometric approach

We report sculptured diverse photonic lattices simultaneously embedded with intrinsic defects of tunable type, number, shape as well as position by a single-step dynamically reconfigurable fabrication approach based on a programmable phase spatial light modulator-assisted interference lithography. The presented results on controlled formation of intrinsic defects in periodic as well as transversely quasicrystallographic lattices, irrespective and independent of their designed lattice geometry, portray the flexibility and versatility of the approach. The defect-formation in photonic lattices is also experimentally analyzed. Further, we also demonstrate the feasibility of fabrication of such defects-embedded photonic lattices in a photoresist, aiming concrete integrated photonic applications.

Two‐stage logarithmic converter with reduced memory requirements

This study presents an efficient method for converting a normalised binary number x (1 ≤ x <; 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.

Efficient compilation of CUDA kernels for high-performance computing on FPGAs

The rise of multicore architectures across all computing domains has opened the door to heterogeneous multiprocessors, where processors of different compute characteristics can be combined to effectively boost the performance per watt of different application kernels. GPUs, in particular, are becoming very popular for speeding up compute-intensive kernels of scientific, imaging, and simulation applications. New programming models that facilitate parallel processing on heterogeneous systems containing GPUs are spreading rapidly in the computing community. By leveraging these investments, the developers of other accelerators have an opportunity to significantly reduce the programming effort by supporting those accelerator models already gaining popularity. In this work, we adapt one such language, the CUDA programming model, into a new FPGA design flow called FCUDA, which efficiently maps the coarse- and fine-grained parallelism exposed in CUDA onto the reconfigurable fabric. Our CUDA-to-FPGA flow employs AutoPilot, an advanced high-level synthesis tool (available from Xilinx) which enables high-abstraction FPGA programming. FCUDA is based on a source-to-source compilation that transforms the SIMT (Single Instruction, Multiple Thread) CUDA code into task-level parallel C code for AutoPilot. We describe the details of our CUDA-to-FPGA flow and demonstrate the highly competitive performance of the resulting customized FPGA multicore accelerators. To the best of our knowledge, this is the first CUDA-to-FPGA flow to demonstrate the applicability and potential advantage of using the CUDA programming model for high-performance computing in FPGAs.

Floating Gate-Based Field Programmable Mixed-Signal Array

We present the field programmable array of analog and digital devices (FPAADD) as a novel implementation of a field programmable mixed-signal array (FPMA). The FPAADD is a hybrid combination of a field programmable analog array (FPAA) and a field programmable gate array (FPGA). Unlike other FPMAs where the FPGA and FPAA portions are kept separate, this architecture closely integrates the two in a fine-grained interleaved array. Instead of using hard-coded data converters, the FPAADD synthesizes data converters out of its reconfigurable fabric. The analog and digital portions share a common global interconnect. Floating gate (FG) transistors are used as the switch and memory elements of the chip, providing better switch performance and power over traditional static random-access memory-based approaches. The precise programmability of the FG switches also allows for computation to take place in the interconnect. These key differences make the FPAADD much more general purpose than previous FPMA architectures. The FPAADD consists of 27 × 8 array of 108 digital and 108 analog tiles and peripheral circuitry on 5 × 5 mm2 die fabricated in a 0.35- μm CMOS process, and contains more than 130 000 FG transistors.

Test Strategies for Reliable Runtime Reconfigurable Architectures

Field-programmable gate array (FPGA)-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects. To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the reconfigurable fabric. This can be achieved by periodic or on-demand online testing. This paper presents a reliable system architecture for runtime-reconfigurable systems, which integrates two nonconcurrent online test strategies: preconfiguration online tests (PRET) and postconfiguration online tests (PORT). The PRET checks that the reconfigurable hardware is free of faults by periodic or on-demand tests. The PORT has two objectives: It tests reconfigured hardware units after reconfiguration to check that the configuration process completed correctly and it validates the expected functionality. During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic. Altogether, this paper presents PRET, PORT, and the system integration of such test schemes into a runtime-reconfigurable system, including the resource management and test scheduling. Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.

Reconfigurable fabrication of scattering-free polymer network liquid crystal prism/grating/lens

We report a simple reconfigurable printing method for fabricating submillisecond-response and scattering-free polymer network liquid crystal photonic devices, such as prism, grating, and lens. To suppress light scattering in the visible region, we reduce the domain sizes by controlling polymer concentration, selecting a high viscosity liquid crystal (LC) host, and performing UV curing at a low temperature. To demonstrate the configurability, we printed a LC micro-prism array with ∼300-μm feature size and a circular lens with 1.3-mm radius without any pre-patterned templates. This reconfigurable printing technique enables fast design iterations and should have widespread applications for fabricating display and photonic devices.

Cell-Based Architecture for Adaptive Wiring Panels: A First Prototype

Wepresent a first prototype for developing the concept of amanifold of adaptive wiring cells connected as a single overall adaptive wiring panel. Themain use of the adaptive wiring panel is related to affordable plug-and-play space applications. A reconfigurable switch fabric enables dynamic routing of signals and power; thus, power, digital, and analog signals can be routed for space systems. This concept can also be applied to terrestrial applications such as aircraft wiring and ground-based systems. The adaptive wiring panel is a manifold of adaptive wiring cells cast as a single overall panel. The panel is a pegboard-like structure, which does not articulate specific sockets, but rather provides a continuous grid of contact pads and mechanical mounting holes. Implementation is based on three basic elements: 1) cell units, which are minimum independent units of the adaptive wiring panel, each with interconnections and links with other cells to form the switch fabric by which wewire components to each other; 2) a cell management unit, which talks independently with all cell units and manages the wiring path and panel switch connections; and 3) modules that provide the components to be wired.

Implementation of comprehensive address generator for digital signal processor

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log 2 N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Ionizing Radiation Detector for Environmental Awareness in FPGA-Based Flight Computers

Ionizing radiation has a detrimental effect on digital electronics which need to operate in extraterrestrial environments. Modern reconfigurable digital fabrics are enabling new architectures for flight computers, which can exploit environmental awareness to increase their fault tolerance. In this paper, we present the design, modeling, and characterization of a radiation sensor which can be coupled with a reprogrammable hardware fabric to provide spatial information about radiation events that can cause logical faults. The sensor uses a wide area PN junction as its fundamental sensing element. As radiation passes through the sensor, electron hole pairs are created. The internal electric field of the PN junction sweeps the charge carriers in opposite directions which are ultimately sensed by orthogonally placed electrodes on the top and bottom of the sensor. This XY grid provides the spatial location of an ionizing radiation strike, which can be fed to the coupled computer fabric for environmental awareness. A reverse bias voltage is applied to the sensor in order to fully deplete the substrate for maximum charge carrier generation. The sensor is designed to detect the spatial location of radiation strikes of energy levels, which can cause faults in commercial field programmable gate arrays substrates.

Evaluation of the Stretch S6 Hybrid Reconfigurable Embedded CPU Architecture for Power-Efficient Scientific Computing

Embedded CPUs typically use much less power than desktop or server CPUs but provide limited or no support for floating-point arithmetic. Hybrid reconfigurable CPUs combine fixed and reconfigurable computing fabrics to balance better execution performance and power consumption. We show how a Stretch S6 hybrid reconfigurable CPU (S6) can be extended to natively support double precision floating-point arithmetic. For lower precision number formats, multiple parallel arithmetic units can be implemented. We evaluate if the superlinear performance improvement of floating-point multiplication on reconfigurable fabrics can be exploited in the framework of a hybrid reconfigurable CPU. We provide an in-depth investigation of data paths to and from the S6 reconfigurable fabric and present peak and sustained throughput as a function of wide registers used and total operand size. We demonstrate the effect of the given interface when using a floating-point fused multiply-accumulate (FMA) SIMD unit to accelerate the LINPACK benchmark. We identify a mismatch between the size of the S6s reconfigurable fabric and the available interface bandwidth as the major bottleneck limiting performance which makes it a poor choice for scientific workloads relying on native support for floating-point arithmetic.

A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs

This paper presents a novel design flow for the implementation of digital systems onto SRAM-based FPGAs with soft error mitigation properties. Traditional fault detection/tolerance techniques are coupled with the device dynamic reconfiguration property to achieve soft error mitigation capabilities, and are applied to the single component, to groups of components or to the entire system, based on the most convenient trade-off with respect to a set of parameters. The design flow performs a two-steps multiobjective design space exploration, driven by a cost function taking into account resource utilization, area, and reconfiguration time. A floorplanning based on precise FPGA resource models is introduced to guarantee the feasibility of the hardened solution, identifying a convenient mapping onto the heterogeneous reconfigurable fabric. Experimental results show that the achieved solutions, aimed at achieving a prompt, "on demand” recovery when fault occurs, are characterized by a reduction in reconfiguration time that is higher than 80 percent, a significant improvement with respect to classical solutions.