Reconfigurable Bit Research Articles

Design and implementation of the Walsh-Hadamard transform on a ternary optical computer.

Walsh-Hadamard is a commonly used mathematical transformation, a mathematical method for spectrum analysis in the real number domain, which has been widely used in many fields such as digital signal processing, spectral modulation, and image processing. Based on the characteristics of the ternary optical computer with a large number of processor bits, reconfigurable bit functions, and parallel computation, a ternary optical processor with all bits allocated is given, and the transformations T,W,T',W',T2 of modified signed-digit (MSD) addition are reconfigured. On this basis, by configuring AdderN MSD adders on the optical processor, the N-point Walsh-Hadamard transform fast parallel computing approach is given. It requires only 3×⌊N/AdderN⌋ clock cycles to compute the Walsh-Hadamard transform of N points under parallel computing. Furthermore, complexity analysis shows that the clock cycles in an electronic computer are N/3 times that of in a ternary optical computer under the fully parallel optical computation. The experiment of the Walsh-Hadamard transform with eight points shows that parallel optical computing has more advantages than the conventional electronic computer in fast computing the problems with characteristics of parallel computing. At the same time, it highlights the advantages and potential of ternary optical computers in data-intensive computing.

Soliton dynamics of ring quantum cascade lasers with injected signal

AbstractNonlinear interactions in many physical systems lead to symmetry breaking phenomena in which an initial spatially homogeneous stationary solution becomes modulated. Modulation instabilities have been widely studied since the 1960s in different branches of nonlinear physics. In optics, they may result in the formation of optical solitons, localized structures that maintain their shape as they propagate, which have been investigated in systems ranging from optical fibres to passive microresonators. Recently, a generalized version of the Lugiato–Lefever equation predicted their existence in ring quantum cascade lasers with an external driving field, a configuration that enables the bistability mechanism at the basis of the formation of optical solitons. Here, we consider this driven emitter and extensively study the structures emerging therein. The most promising regimes for localized structure formation are assessed by means of a linear stability analysis of the homogeneous stationary solution (or continuous-wave solution). In particular, we show the existence of phase solitons – chiral structures excited by phase jumps in the cavity – and cavity solitons. The latter can be deterministically excited by means of writing pulses and manipulated by the application of intensity gradients, making them promising as frequency combs (in the spectral domain) or reconfigurable bit sequences that can encode information inside the ring cavity.

A mission oriented reconfiguration technology for Spaceborne FPGA

Reconfigurable technology based on FPGA is increasingly used in satellites to meet the demand of the increasing missions that satellites need to complete in recent years. In this paper, a mission oriented reconfiguration technology for spaceborne FPGA is introduced to address the problem that how to meet the demand of satellite reconfiguration mission to orbit, execution time and FPGA resource requirements. Satellite reconfiguration system is divided into three parts, that is, mission management module, reconfiguration management module and reconfigurable FPGA. Firstly, a mission list is set up to record the mission’s execution time and space attributes, hardware space attributes and priority attributes. The mission is allocated to the FPGA resource area correspondingly based on the flexible region model. According to the time attribute and priority attribute of the mission, the reconfiguration management module carries out the reconfiguration action. And the reconfiguration management module mainly deals with reconfiguration library management and the entire or partial reconfiguration according to the configuration file. After the reconfigurable bit files are loaded to FPGA, the transformation and execution of the hardware resources from the mission to the hardware are completed. Finally, an evaluation of the real-time performance, reliability and security of the design is carried out. Experiments that based on a verification system composed of raspberry/PI and ZYNQ are conducted and results fully prove that the design in this paper can support mission oriented spaceborne FPGA reconfiguration.

Flexible VLSI architectures for Galois field multipliers

Galois field (GF) multipliers play a major role in the engineering applications such as cryptography and error correcting codes. This paper proposes systolic vector m-bit GF(p) and GF(2m) multipliers (m=log2p), where four numbers of m2-bit GF multiplications can be done in parallel. Similarly, twelve and sixteen numbers of GF(2m4) and m4-bit GF(p) multiplications can be done in parallel respectively. Also, this paper proposes non vector flexible GF(2m) and m-bit GF(p) multipliers, where the m can be varied from 2 to the maximum allowable value. Our proposed systolic vector parallel GF(216) multiplier achieves 95.8% of improvement in throughput over reconfigurable bit serial design [7]. Similarly, the proposed systolic vector parallel 16-bit GF(p) multiplier achieves 82.5% of improvement in throughput over reconfigurable bit serial design [23] using 45nm CMOS technology.

Energy-Efficient Hybrid Spintronic–Straintronic Nonvolatile Reconfigurable Equality Bit Comparator

We propose and analyze a “spintronic/straintronic” reconfigurable equality bit comparator implemented with a nanowire spin valve whose two contacts are two-phase multiferroic nanomagnets and possess bistable magnetization. A reference bit is “written” into a stable magnetization state of one contact and an input bit in that of the other with electrically generated strain. The spin-valve’s resistance is lowered (raised) if the bits match (do not match). Multiple comparators can be interfaced in parallel with a magneto-tunneling junction to determine if an [Formula: see text]-bit input stream matches an [Formula: see text]-bit reference stream bit by bit. The system is robust against thermal noise at room temperature and a 16-bit comparator can operate at [Formula: see text][Formula: see text]MHz while dissipating [Formula: see text][Formula: see text]28[Formula: see text]fJ per cycle. This implementation is more energy-efficient than CMOS-based implementations and the reference bits can be stored in the comparator itself without the need for refresh cycles or the need to fetch them from a remote memory for comparison. That improves reliability, speed and security.

Signal monitoring and performance stability evaluation tool in a high speed optical communication network

The diverse communication systems in South Africa have changed drastically over the last few years and are envisioned to continue to improve as evidenced by the deployment of high speed optical fibre networks, in both access and metro networks. The key task in the design of any communication network is to come up with a tool that monitors and evaluates the performance stability of the entire communication link. A cost effective, reliable and reconfigurable bit error ratio (BER) signal analyzer was designed and implemented to monitor and evaluate the overall performance stability of a high speed optical communication link. The reconfigurable digital signal processing (DSP) assisted optical receiver is an alternative technology to the expensive and complex hardware receivers, based on its ability to be repurposed to adapt to different modulation formats. BER is a figure of merit that allows different optical communication systems to be evaluated in a fair and consistent manner. In this experimental work, a reconfigurable DSP signal analyzer tool was developed and implemented to evaluate the performance stability of an unamplified transmission through a 25km G. 655 fibre at 1550nm. The developed DSP algorithm was authenticated and validated by comparing its performance with results obtained from a commercial BER tester. A transmission penalty of 2dB was attained on comparing the back-to-back to a transmission over 25km of fibre. The cost effective DSP assisted receiver is a valuable tool to monitor and evaluate the performance fidelity of a high speed optical communication link.

A Novel Combinatorics‐Based Reconfigurable Bit Permutation Network and Its Circuit Implementation

Bit permutation is an important operation in many applications. A novel reconfigurable N ×N bit permutation network with a compact structure is presented. It is based on combinatorics theory by cascading two recursive N/2 × N/2 sub-networks, while each subnetwork is cascaded by two N/4×N/4 sub-networks, and so on cascaded until reaching the elementary 4 × 4 seed networks. Its routing algorithm is also established to determine each multiplexor’s status. Then the circuits of different sized permutation networks in a reconfigurable cipher co-processor were designed and implemented in 0.18μm CMOS process. The proposed circuit can achieve an arbitrary n × n permutation and support all types of bit permutations in many cryptographic algorithms. Plus, it consumes less multiplexors than commonly used BENES and OMFLIP networks.

Performance Improvement of DPSK Signal Reception Using Reconfigurable Multiple Bit Differential Detection in the Presence of Carrier Frequency Offset

In this paper we propose a reconfigurable multiple bit differential detection (MBDD) algorithm with diversity reception in the form of postdetection equal-gain combining (EGC) that can be used for the differential phase shift keying (DPSK) signal reception in the presence of significant frequency offsets. The proposed algorithm is based on the MBDD algorithm with the introduction of a mechanism for the estimation of the frequency offset. The algorithm is checking N c frequency offsets around zero offset and chooses the one that is the most likely. The analysis shows that the receiver with the proposed algorithm provides signal reception with almost equal quality in a wide range of carrier frequency offsets around zero frequency offset.

Bit plane matching based variable block size motion estimation method and its hardware architecture

Variable Block Size Motion Estimation (VBSME) is one of the most important features of state-of-theart video encoders. In the H.264/AVC encoder, the computational complexity of integer motion estimation is about 75%. Therefore, reducing this complexity is one of the key points to provide low power video encoding. In this paper, a reconfigurable bit plane matching based VBSME method and a runtime reconfigurable hardware architecture are proposed to allow low-power consumer electronic devices to make a trade-off between power requirements and motion estimation (ME) accuracy. The proposed ME method is the only low complexity ME algorithm proposed in the literature so far that can provide compatible ME accuracy for lower block sizes compared to the sum of absolute difference (SAD) criterion. A new data path for the computation of the matching criterion in the proposed hardware architecture which has a fully arithmetic structure is proposed to improve the previously utilized LUT based architectures by having a fully arithmetic structure.

Reducing Conflict Misses by Application-Specific Reconfigurable Indexing

The predictability of memory access patterns in embedded systems can be successfully exploited to devise effective application-specific cache optimizations. In this paper, an improved indexing scheme for direct-mapped caches, which drastically reduces the number of conflict misses by using application-specific information, is proposed. The indexing scheme is based on the selection of a subset of the address bits. With respect to similar approaches, the solution has two main strengths. First, owing to an analytical model for the conflict-miss conditions of a given trace, it provides a symbolic algorithm to compute the optimum solution (i.e., the subset of address bits to be used as cache index that minimize the number of conflict misses). Second, owing to a reconfigurable bit selector that can be programmed at run time, it allows the optimal cache indexing to fit to a given application. Results show an average reduction of conflict misses of 24%, measured over a set of standard benchmarks, and for different cache configurations