Power Consumption Of Receiver Research Articles

RF Power Gating: A Low-Power Technique for Adaptive Radios

In this paper, we propose a low-power technique, called RF power gating, which consists in varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on the bit error rate (BER) performances is studied for a basic estimator in the specific case of minimum-shift keying signaling. A system-level energy model is also derived and discussed to estimate precisely the power reduction based on the characteristics and the power consumption of each block. This model allows highlighting the different contributors of the power reduction. The BER results and the energy model are finally merged to determine the best ATR meeting the design constraints. Applying this technique to the IEEE 802.15.4 standard, this paper shows that an ATR of 20% is a good tradeoff to meet the packet error rate constraint while maximizing the energy reduction ratio. Using typical block power consumptions, an energy reduction ratio around 20% can be reached. Even better energy reduction ratios ( $\sim 60$ %) are also achievable when most of the blocks are power-gated.

An Ultra-Low-Power RF Energy-Harvesting Transceiver for Multiple-Node Sensor Application

An ultra-low-power wirelessly powered radiofrequency (RF) transceiver for wireless sensor network is implemented using 180-nm CMOS technology. We propose a 98- $\mu\mbox{W}$ 457.5-MHz transmitter with output radiation power of $-$ 22 dBm. This transmitter utilizes 915-MHz wirelessly powering RF signal by frequency division using a true-single-phase-clock divider to generate the carrier frequency with very low power consumption and small die area. The transmitter can support up to 5-Mb/s data rate. The telemetry system uses an eight-stage Cockcroft–Walton rectifier to convert RF to dc voltage for energy harvesting. The bandgap reference and linear regulators provide stable dc voltage throughout the system. The receiver recovers data from the modulated wireless powering RF signal to perform time-division multiple access (TMDA) for the multiple-node system. Power consumption of the TDMA receiver is less than 15 $\mu\mbox{W}$ . Our proposed transmitter and receiver each occupies 0.0018 and 0.0135 mm 2 of active die area, respectively.

An Optimized Low-Power-Consumption Tracking Algorithm Based on Navigation Message Structure for Weak Signals

In order to reduce the power consumption of handset GNSS receivers, we present a novel algorithm that tracks signals at fixed positions of the navigation message in an intermittent mode. The tracking channels only run during the beginning part of the message frame. In the rest they remain in idle state, to reduce power consumption of the channel. The beginning position of each message frame can be estimated accurately, and the beginning messages are constant or can be estimated, thus the coherent integration time can exceed one navigation bit, which can improve the Doppler frequency estimated accuracy. At the fixed position of the frame, the tracking channel only tracks the pseudo-code phase, and does not track the carrier frequency and phase. This algorithm can keep stable tracking for weak signals with 28 dBHz carrier-to-noise ratio (C/N0), while using only 2% of the power required by the computation associated with the traditional tracking.

Analysis of uncertainty in visibilty samples via average correlation in a synthetic aperture interferometric radiometer

Synthetic aperture interferometric radiometry (SAIR) has provided an effective approach for achieving high spatial resolution in remote sensing at microwave frequencies. The radiometric sensitivity of a synthetic aperture interferometric radiometer is determined by the uncertainty in visibility samples. Generally, visibility samples can be calculated by utilizing either nominal or redundant correlation methods, such as in microwave imaging radiometry with aperture synthesis. In this paper, we use the average of results from both methods, which results in a 1.5 dB improvement in the signal-to-noise ratio (SNR) of visibility samples by assuming double side band (DSB) inphase/quadrature (I/Q) demodulation. Moreover, the requirement for the baseband signals to have a high sampling rate for optimum visibility sample uncertainty can be greatly relaxed, regardless of the type of demodulation. The receiver complexity, volume, and power consumption will be also much lower, which is critical for airborne and space-borne SAIR applications. The mathematical derivation is presented in detail followed by verifications with several experiment results based on the SAIR prototype instrument.

2.4 GHz discrete‐time receiver without subsampling mixer

A subsampling filter is proposed for a discrete-time receiver (DTR). This filter achieves signal discretisation, filtering and downconversion simultaneously. With the proposed subsampling filtering technique, the subsampling mixer in a conventional DTR is eliminated, which can reduce power, cost and noise. The first 2.4 GHz DTR prototype for Zigbee application is fabricated in a 0.18 μm CMOS process. It achieves 23 dB conversion gain, 17.6 dB noise figure and -15 dBm IIP3. Operated from a single 1 V supply, the low-noise amplifier and following filter stages consume only 3.8 mW and the total receiver power consumption is 25.6 mW.

An Ultra Low Energy FSK Receiver With In-Band Interference Robustness Exploiting a Three-Phase Chirped LO

An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It features improved in-band interference tolerance by chirping the transmission frequency. To reduce the receiver power consumption, a novel three-phase passive mixer along with a three stage digitally controlled ring oscillator is proposed, while still allowing quadrature detection. A mixer-first direct conversion receiver architecture moves the required gain to lowest frequency and lowest bandwidth to reduce power consumption. A low power flip-flop based BFSK demodulator is proposed that reduces the baseband power further. The receiver is designed and fabricated in a 65 nm complementary metal-oxide-semiconductor process. It consumes 219 μW from 1.2 V power supply, while having a sensitivity of -70 dBm for a bit error rate of 0.1% at 2.4 GHz. Except the off-chip 64 MHz clock generation, the total receiver requires 27 pJ/bit. Using a chirped clock spreading of 360 MHz and chirp repetition rate of 1 MHz, it can tolerate up to -8 dB signal to interference ratio for all interferer frequencies. This is 13.5 dB better than previously reported in literature and 12 dB better than ideal noncoherent BFSK receiver interference robustness.

A New Energy-Aware Source Routing Protocol for Maximization of Network Lifetime in MANET

In this letter, we propose an energy-aware source routing protocol for maximizing the network lifetime in mobile ad hoc networks. We define a new routing cost by considering both transmit and receive power consumption and remaining battery level in each node simultaneously and present an efficient route discovery procedure to investigate the proposed routing cost. Intensive simulation verifies that the proposed routing protocol has similar performance to the conventional routing protocols in terms of the number of transmission hops, transmission rate, and energy consumption while significantly improving the performance with respect to network lifetime.

Communication controller and control unit design for Qi wireless power transfer

Abstract Qi, the wireless power standard, has been proposed to allow low power systems to receive power through wireless inductive power transfer. The standard outlines the essential, desired and optional requirements for developing the wireless power transfer platform. In this paper, we present the design and implementation results of communication controller for guided positioning single transmitter–single receiver wireless power transfer platform. Apart from the basic design, additional processing and data storage capability is introduced to make the design adaptive in terms of response time and the size of control data transfer. The method of estimating the amount of power transfer is modified to reduce design complexity and internal power consumption of power transmitter and receiver. The implementation results help to access the ratio of power transferred to resource utilization and the ratio of power transferred to power consumed in simplistic wireless power transfer platform.

A 4.4-$\mu$W Wake-Up Receiver Using Ultrasound Data

In wireless sensor nodes, using a wake-up receiver to duty-cycle the main receiver significantly reduces the overall power consumption of the node, as long as the power consumption of the always-ON wake-up receiver is very low. We demonstrate line-of-sight ultrasound data communications for ultra-low power wireless wake-up in sensor networks. The 65-nm CMOS 0.6-V receiver prototype achieves a BER of better than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> measured for a 250-bps free-space 8.6-m link in an indoor environment while dissipating only 4.4 μ W and requiring only - 18 dBm electrical power to be delivered to the transmit transducer.

A 915 MHz, Ultra-Low Power 2-Tone Transceiver With Enhanced Interference Resilience

An ultra-low-power RF envelope-detection radio has been designed for low-power short-range wireless applications. It introduces an interference rejection technique that improves the in-band selectivity by 24.5 dB. The transmitter adopts the power-efficient direct-modulation architecture, and the receiver maintains the simplicity and low power consumption of envelope detection receivers. In the 915 MHz ISM band at 10 kbps the transmitter output level reaches - 3 dBm with 33.9% global efficiency, while the receiver achieves -83 dBm sensitivity with 121 μW power consumption. The Tx and Rx implemented in 90 nm CMOS technology occupy 0.71 and 1.27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

PERFORMANCE COMPARISON OF ED, TR AND DTR IR-UWB RECEIVERS FOR COMBINED PAM-PPM MODULATION IN REALISTIC UWB CHANNELS

This paper studies the bit error rate (BER) performance of non-coherent impulse-radio ultra wideband (IR-UWB) correlation receivers in the IEEE 802.15.3a channel for combined binary pulse amplitude modulation-pulse position modulation (BPAM-PPM) scheme. The BER performance is based on the channel averaged signal-to-noise ratio (SNR). The study includes simple transmitted reference (TR), difierential TR (DTR), and energy detection (ED) receiver structures. Moreover, difierent performance parameters are addressed, namely the signal bandwidth integration window factor, number of pulses per bit, and receiver power consumption. ED receivers with BPAM-PPM are shown to outperform simple TR receivers and have a performance which approaches that of difierential TR (DTR) receivers with smaller power consumption for the same design parameters.

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

A 3-5 GHz UWB radar chip in 0.13 ㎛ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme

In this article, a 3.2 Gb/s serial link transceiver, that can be implemented in 0.35 μm CMOS technology is presented. In this transceiver a new multi-level pulse-width-amplitude modulation technique is used. The symbol rate is reduced, while the minimum pulse width (PW) is increased considerably, using the proposed modulation. The PW is larger than the conventional NRZ data format, with PW of Tb, so the ISI will be improved. The multiphase output of a three stage ring oscillator VCO in the PLL is used to modulate and to demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down paths. The peak to peak jitter of recovered clock is 21 ps at 800 MHz. The recovered data has the peak to peak jitter of 51 ps. The transmitter and receiver power consumption is 220 and 35 mW, respectively.

A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver

A 1.2 V 100 Mb/s 2.93 mW discrete-time charge-domain impulse radio ultra-wideband (IR-UWB) receiver is developed in 65 nm CMOS. In the charge-domain, the template of the correlator is represented by capacitance and the correlation is implemented by charge addition instead of voltage multiplication and voltage integration. Power consumption of the charge-domain receiver is minimized by a novel auto- and cross-correlation based synchronization scheme. To reduce the power consumption and the chip area of the PLL clock generator for the receiver, a dual charge-pump PLL is proposed to scale up the capacitance of the loop filter without extra charge-pump current. The developed UWB receiver with the area- and power-efficient PLL achieves the energy consumption of 29.3 pJ/bit with the 62.5-ps timing step for data synchronization.

A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing

This paper presents a sub-Nyquist rate sampling receiver architecture that exploits signal sparsity by employing compressive sensing (CS) techniques. The receiver serves as an analog-to-information conversion system that works at sampling rates much lower than the Nyquist rate. A parallel-path structure that employs current mode sampling techniques is used. The receiver performance is quantified analytically. Useful and fundamental design guidelines that are unique to CS are provided based on the analytical tools. Simulations with a 90-nm CMOS process verify the theoretical derivations and the circuit implementations. Based on these results, it is shown that an instantaneous receiver signal bandwidth of 1.5 GHz and a signal-to-noise-plus-distortion ratio of 44 dB are achievable. The receiver power consumption is estimated to be 120.8 mW. A comparison with state-of-the-art high-speed analog-to-digital conversions reveals that the proposed approach improves the figure of merit by a factor of three if the signal exhibits a 4% sparsity.

An improved transient-type ice-penetrating radar

AbstractA low-cost, compact, short-pulse ice-penetrating radar (IPR) system with a center frequency of 50 MHz for sounding glacier topography is presented. The radar was developed to measure ice thickness and to image internal structures and basal conditions of glaciers and ice sheets with a maximum range of ∼16000 ns and a depth resolution better than 2.5 m. The receiver of the IPR system employs asynchronous operation mode, avoiding the need for a cable between the transmitter and receiver. A new sampling technology using a high-speed field programmable gate array, which implements a 256-trace stacking algorithm to realize the analog-to-digital conversion, both simplifies the structure of the receiver and increases the sampling efficiency. The power consumption of the whole receiver is &lt;1.5 W, which can be supplied by a laptop computer. Test measurements were made during the 5th China Expedition to the Grove Mountains in East Antarctica. Field tests show the capability of this system to measure ice thickness up to 650 m and to define internal layers within the ice body.

A Bandpass Sampling Design in Multi-channel Radio Receiver

Abstract Bandpass sampling is a special form of undersampling that translates a high frequency bandpass signal to baseband frequency. The required sampling frequency depends on the signal bandwidth, rather than on its highest frequency component. Some bandpass sampling methods are used to solve the power consumption of a multi-channel radio Receiver. The experiments show that the bandpass sampling design can significantly reduce power consumption without suffering any performance lost.

Co-Channel Interference Cancellation Using Single Radio Frequency and Baseband Chain

We present a new architecture for multi-antenna receivers that cancels the co-channel interference (CCI) using a single radio frequency (RF) and baseband (BB) chain, while still achieving nearly the same bit error rate that can be provided by the conventional receiver architecture requiring multiple RF/BB chains. The proposed receiver architecture enables multiple transmitter-receiver pairs to simultaneously communicate in the same frequency band without additional bandwidth, thereby increasing the spectral efficiency or capacity, with significantly reduced receiver complexity and power consumption.

Unequal decoding power allocation for efficient video transmission

We present an unequal decoding power allocation (UDPA) approach for minimization of the receiver power consumption subject to a given quality of service (QoS), by exploiting data partitioning and turbo decoding. We assign unequal decoding power of forward error correction (FEC) to data partitions with different priority by jointly considering the source coding, channel coding and receiver power consumption. The proposed scheme is applied to H.264 video over additive white Gaussion noise (AWGN) channel, and achieves excellent tradeoff between video delivery quality and power consumption, and yields significant power saving compared with the conventional equal decoding power allocation (EDPA) approach in wireless video transmission.

Design of pre-processing algorithms for efficient MIMO–OFDM receiver architectures

Modern wireless communication applications are characterized by the need for advanced signal processing techniques such as Multiple-Input Multiple-Output (MIMO) technology for achieving high throughput and diversity and Orthogonal Frequency Division Multiplexing (OFDM) for achieving robustness to multipath fading. The implementation of such techniques at the transceiver level typically involves the design of algorithms with high processing complexity. This paper considers the efficient design of MIMO–OFDM receivers in preamble-based systems and addresses the problem of large processing delays associated with pre-computations and symbol detection. The existence of large processing delays has a huge impact on the performance and resource requirements (vector processing, increased clock rates and increased power consumption) of modern receivers. More specifically, we address the performance and complexity bottleneck introduced by the pre-computations involved for MIMO–OFDM channel decomposition. We propose a redesign of channel decomposition algorithms which achieves a better matching of the processing rate of MIMO–OFDM receivers to the real-time processing deadlines imposed by the structure of the incoming data packets. It is demonstrated that for a specific MIMO-OFDM channel training frame structure (alternating antenna preamble), simple modifications to typical channel decomposition algorithms can achieve significant processing performance and complexity gains compared to typical receiver designs.