In this paper, the authors propose a new parallel rotator for FFT and IFFT applied in multi-carrier radio communication systems. The proposed algorithm serves some primary purposes. First, it reduces the computational complexity, thus simplifying the hardware implementation. Second, it speeds up the convergence of the algorithm, resulting in reduced processing latency to meet the requirements of real-time services. Third, it improves rotational accuracy. In addition, the algorithm also significantly lessens the consumption of hardware and power resources. The phase rotator's hardware architecture is then proposed and implemented on the FPGA using the Vivado System Generator for DSP Tool (SYSGEN). The FPGA experimental results indicate that the proposed algorithm's computational complexity, processing delay, and hardware resource usage are significantly reduced when compared to some recent algorithms.