Real-time Guarantees Research Articles

Hard real-time guarantees in feedback-based resource reservations

Resource reservation is a technique that allows isolating applications from interfering among each other. In the most classic setting, this method requires the periodic allocation of a given budget of resource over time. However, in reality, the actual budget allocation may deviate from its ideal value. Examples of causes of this deviation are: the presence of a system tick, the usage of shared resources, the self-blocking on I/O operations, etc. Since control techniques are an effective mean to deal with uncertainties and disturbances, unknown at design time but bounded, in this paper we propose to use feedback to achieve the target budget allocation, which may have deviated due to on-line events. The proposed scheme, called Self-Adaptive Server (SAS), is described and analyzed. We prove that the controller gain, which maximizes the resource delivered to the application, is $$\frac{3-\sqrt{5}}{2}$$3-52. We also implemented the scheduler on a lightweight operating system for a microcontroller. Thanks to the extremely simple implementation, SAS servers are well suited for low-overhead resource isolation mechanisms with proved real-time guarantees.

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. We demonstrate the real-time guarantees on bandwidth and latency provided by our multichannel memory controller architecture by experimental evaluation. Furthermore, we compare the performance of the mapping problem formulation in a solver and the heuristic algorithm against two existing mapping algorithms in terms of computation time and mapping success ratio. We show that an optimal solution can be found in 2 hours using the solver and in less than 1 second with less than 7% mapping failure using the heuristic for realistically sized problems. Finally, we demonstrate configuring a Wide IO DRAM in a high-definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of this work.

Constant bandwidth server revisited

The Constant Bandwidth Server (CBS) is an algorithm for providing temporal protection and real-time guarantees to real-time sporadic tasks. Recently, an implementation of this algorithim called SCHED_DEADLINE has been included in the Linux kernel. Therefore, the CBS algorithm is now used to serve more generic tasks than do not obey to the classical sporadic task model. One important type of tasks which was not considered by the original CBS algorithm is the so called "self-suspending task model", where a task instance can suspend itself waiting for an external event. Even if the original algorithm is adapted so that the temporal protection property continues to hold, it is difficult for developers to provide guarantees and to select the most appropriate server parameters for such tasks. This paper investigates the problem of using the CBS algorithm for serving self-suspending tasks, by analysing it from a theoretical point of view and showing how to select the server parameters (budget and periods) for self-suspending tasks. Finally, the effectiveness of these proposals is shown through both simulations and real experiments on Linux / SCHED_DEADLINE.

Location-Based Data Aggregation in 6LoWPAN

Location-based information has recently been exploited to assist the aggregated process of data, thereby reducing the spatial redundancy efficiently. The constraints nature in 6LoWPAN becomes one of the major concerns in data aggregation methods. However, traditional CSMA/CA in MAC layer may cause significant transmission and control overhead as well as delay on listening and competing for channels. It is a low efficient way to transfer IPv6 packet due to the big packet header. To overcome these shortages, in this paper, we propose LDAA, a location-based novel data aggregation model that aggregates data from the network layer according to the MAC layer queuing delay. When the queuing delay becomes larger, more packets will be dynamically aggregated into one packet to increase the proportion of application data. Otherwise, the amount of packets involved in aggregation will decrease to improve channels utilization. Simulation results show that our approach could provide better real-time guarantees and reduce data spatial redundancy and energy consumption efficiently.

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high performance to react in front of infrequent particular events as well as extreme energy efficiency in order to extend battery lifetime during most of the time when low performance is required. In addition, they require real-time guarantees. The most suitable technological solution for these devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/subthreshold voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and trading off different SRAM designs is mandatory. This is particularly true for cache memories, which occupy most of the processor's area. In this article, we propose new, simple, single-Vcc-domain hybrid L1 cache architectures suitable for reliable hybrid high and ultra-low voltage operation. In particular, the cache is designed by combining heterogeneous SRAM cell types: some of the cache ways are optimized to satisfy high-performance requirements during high voltage operation, whereas the rest of the ways provide ultra-low energy consumption and reliability during near-/subthreshold voltage operation. We analyze the performance, energy, and power impact of the proposed cache designs when using them to implement L1 caches in a processor. Experimental results show that our hybrid caches can efficiently and reliably operate across a wide range of voltages, consuming little energy at near-/subthreshold voltage as well as providing high performance at high voltage without decreasing reliability levels to provide strong performance guarantees, as required for our target market.

Performance-constrained energy reduction in data centers for video-sharing services

Energy saving in large-scale video sharing data centers is an important yet daunting challenge due to the conflicting goal of providing real-time guarantees. Simple energy reduction techniques can result in excessive delay and severely affect the quality-of-service. This paper aims to optimize energy consumption while ensuring service delay constraints in data centers that provide large-scale video-sharing services. However, this broader goal requires three challenges that must be holistically addressed rather than in isolation. First, we propose a generic model to accurately characterize the disk behavior in a VSS by taking into account the unique characteristic of parallel video workloads. Second, the paper proposes a prediction-based algorithm that formulates and solves a constrained optimization problem for determining optimal selections of disk power modes in VSSs. Third, two novel caching algorithms are proposed that achieve additional energy saving through optimizing cache utilization. Experiments reveal that the proposed 3-component scheme achieves a significant amount of energy saving under the same delay level as compared to traditional energy management schemes.

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

The increasing demand for highly miniaturized battery-powered ultralow cost systems (e.g., below 1 dollar) in emerging applications such as body, urban life and environment monitoring, and so on, has introduced many challenges in chip design. Such applications require high performance occasionally and very little energy consumption during most of the time to extend battery lifetime. In addition, they require real-time guarantees. Caches have been shown to be the most critical blocks in these systems due to their high energy/area consumption and hard-to-predict behavior. New, simple, hybrid-voltage operation (high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> and ultralow V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> ), single-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> domain L1 cache architectures based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with error detection and correction codes have been recently proposed. Such designs provide significant energy and area efficiency without jeopardizing reliability levels to still provide strong performance guarantees. In this brief, we analyze the efficiency of these designs during ultralow voltage operation. We identify the limits of such approaches by finding an energy-optimal voltage region through experimental models. The experimental results show that area efficiency is always achieved in the range 200-400 mV, whereas both energy and area gains occur above 250 mV, i.e., in near-threshold regime.

Real-Time Network Coding for Live Streaming in Hyper-Dense WiFi Spaces

Consumer demand for high-quality video over wireless networks is increasing at fast pace. The resulting technical challenges are particularly stringent in crowded spaces, where the density of users far exceeds the ability to deploy cellular base stations or WiFi infrastructure in a cost effective way. To address this problem, we present a reliable and scalable live streaming solution based on wireless multicast with real-time network coding. At the core of our approach is a timely delivery scheme that uses a minimum amount of feedback from the receivers to generate coded repair packets that are simultaneously useful to a large number of users. Our protocol, which we implemented and tested in a real-world wireless testbed, differs from traditional wireless unicast and multicast schemes in that (a) the feedback messages of the users are treated jointly and (b) the repair mechanism considers both the playout deadlines of individual packets and the list of packets already received by the clients. In comparison with a standard video approach that sends an MPEG-2 encoded stream over 802.11 unicast links, our solution offers real-time guarantees for all users commensurate with the link quality and an 11x improvement in terms of bandwidth usage. A commercial version of the proposed solution shows a strong increase in the number of clients that can access video streams simultaneously over a single WiFi hotspot.

Parallel gesture recognition with soft real-time guarantees

Using imperative programming to process event streams, such as those generated by multi-touch devices and 3D cameras, has significant engineering drawbacks. Declarative approaches solve common problems but so far, they have not been able to scale on multicore systems while providing guaranteed response times.We propose PARTE, a parallel scalable complex event processing engine that allows for a declarative definition of event patterns and provides soft real-time guarantees for their recognition. The proposed approach extends the classical Rete algorithm and maps event matching onto a graph of actor nodes. Using a tiered event matching model, PARTE provides upper bounds on the detection latency by relying on a combination of non-blocking message passing between Rete nodes and safe memory management techniques.The performance evaluation shows the scalability of our approach on up to 64 cores. Moreover, it indicates that PARTE's design choices lead to more predictable performance compared to a PARTE variant without soft real-time guarantees. Finally, the evaluation indicates further that gesture recognition can benefit from the exposed parallelism with superlinear speedups.

Modified Leach in Wireless Sensor Network

Wireless sensor network consists of large number of sensor nodes which is used to capture environmental conditions, process and transfer it to base station. These sensor nodes are sensitive to energy consumption and gets exhausted on working. So we need to emphasize on reducing energy dissipation of sensor nodes in order to improve network lifetime. Various routing protocols are developed to enhance network scalability and stability. The cluster based routing is an efficient way of reducing energy dissipation by limiting data transmission from nodes to base station. For this purpose we proposed a new routing method which improves the life span of network, its data transmitting capability with low energy consumption. It is an improvised version of LEACH protocol which conserves energy by load balancing .Multi hop routing is proposed for the transmission of data. Reduction of energy consumption is achieved with the help of TDMA scheduling. Time division multiple access (TDMA)-based MAC can potentially reduce the delay and provide real-time guarantees as well as save power by eliminating collisions. To keep network alive we had added a random node on replacement of dyeing node. The performance evaluation of protocol is based on simulation test performed in network simulator 2 (NS2) to prove the effectiveness of this proposed method in terms of network lifetime and energy efficiency. Keywords: Base station (BS), Clustering, Energy efficiency, Routing protocol, Wireless sensor network (WS

Adaptive Distributed Data Storage for Context-Aware Applications

Context-aware computing is a paradigm that relies on the active use of information coming from a variety of sources, ranging from smartphones to sensors. The paradigm usually leads to storing large volumes of data that need to be processed to derive higher-level context information. The paper presents a cloud-based storage layer for managing sensitive context data. To handle the storage and aggregation of context data for context-aware applications, Clouds are perfect candidates. But a Cloud platform for context-aware computing needs to cope with several requirements: high concurrent access (all data needs to be available to potentially a large number of users), mobility support (such platform should actively use the caches on mobile devices whenever possible, but also cope with storage size limitations), real-time access guarantees – local caches should be located closer to the end-user whenever possible, and persistency (for traceability, a history of the context data should remain available). BlobSeer, a framework for Cloud data storage, is a perfect candidate for storing context data for large-scale applications. It offers capabilities such as persistency, concurrency and support for flexible storage schema requirement. On top of BlobSeer, Context Aware Framework is designed as an extension that offers context-aware data management to higherlevel applications, and enables scalable high-throughput under high-concurrency. On a logical level, the most important capabilities offered by Context Aware Framework are transparency, support for mobility, real-time guarantees and support for access based on meta-information. On the physical layer, the most important capability is persistent Cloud storage.

Petri Net-Based FTL Architecture for Parametric WCET Estimation via FTL Operation Sequence Derivation

A flash translation layer (FTL) provides file systems with transparent access to NAND flash memory. Although many applications running on it require real-time guarantees, it is difficult to provide tight worst case execution time (WCET) bounds with conventional static WCET analysis since an FTL exhibits a large variance in execution time depending on its runtime state. Parametric WCET analysis could be an effective alternative but it is also challenging to formulate a parametric WCET function for an FTL program because traditional FTL architecture does not properly model the runtime availability of flash resources in its code structure. To overcome such a limitation, we propose Petri net-based FTL architecture where a Petri net explicitly specifies dependencies between FTL operations and the runtime resource availability. It comes with an FTL operation sequencer that derives at runtime the shortest sequence of FTL operations for servicing an incoming FTL request under the current resource availability. The sequencer computes the WCET of the request by merely summing the WCETs of only those FTL operations in the sequence. Our experimental results show the effectiveness of our FTL architecture. It allowed for tight WCET estimation that yielded WCETs shorter by a factor of 54 than statically analyzed ones.

System performance evaluation by combining RTC and VHDL simulation: A case study on NICs

• We combine Real-Time Calculus (RTC) and VHDL simulation for performance evaluation. • We predict analytically NIC’s buffer-size requirements in a network node. • We identify FIFO overflow scenarios by analytic methods. • We present a compositional model of the network-to-memory data path using RTC. • We provide real-time guarantees that are valid up to a certain level of confidence. Analytic models allow the performance evaluation of proposed system changes without requiring complex and expensive detailed simulations. In this paper, Real-Time Calculus (RTC), a high-level analysis technique previously proposed for stream-processing hard real-time systems and frequently used to evaluate trade-offs in packet stream processing architectures, has been applied to analyse the behaviour of network interfaces. Moreover, the simulation of HDL (Hardware Description Language) models has been used to build the RTC descriptions required to analyse the behaviour of these relatively complex systems. As a case study of this proposed combination of Real-Time Calculus and HDL simulation, the prediction of buffer-size requirements and bottlenecks on the Network Interface Card (NIC) of a node receiving Ethernet packets, is also provided. This work intends to increase the efficiency of the performance evaluation of systems by providing real-time guarantees on delays and backlogs that are valid up to a certain level of confidence, as opposed to the hard guarantees commonly derived by formal methods.

Exact and approximate supply bound function for multiprocessor periodic resource model

The Multiprocessor Periodic Resource (MPR) model has been proposed for modeling compositional real-time guarantees of real-time systems which run on a shared multiprocessor hardware. In this paper we extend the MPR model such that the execution of virtual processors (servers) is not assumed to be synchronized i.e., the servers can have different phases. We believe that relaxing the server synchronization requirement provides greater deal of compatibility for implementing such a compositional method on various hardware platforms. We derive the resource supply bound function of the extended MPR model using an algorithm. Furthermore, we suggest an approach to calculate an approximate supply bound function with lower computational complexity for systems where calculating their supply bound function is computationally expensive.

Robust Scheduling of Task Graphs under Execution Time Uncertainty

Effective multicore computing requires to make efficient usage of the computational resources on a chip. Offline mapping and scheduling can be applied to improve the performance, but classical approaches require considerable a priori knowledge of the target application. In a practical setting, precise information is often unavailable; one can then resort to approximate time and resource usage figures, but this usually requires to make conservative assumptions. The issue is further stressed if real-time guarantees must be provided. We tackle predictable and efficient nonpreemptive scheduling of multitask applications in the presence of duration uncertainty. Hard real-time guarantees are provided with limited idle time insertion, by exploiting a hybrid offline/online technique known as Precedence Constraint Posting (PCP). Our approach does not require probability distributions to be specified, relying instead on simple and cheaper-to-obtain information (bounds, average values). The method has been tested on synthetic applications/platforms and compared with an offline optimized Fixed Priority Scheduling (FPS) approach and a pure online FIFO scheduler; the results are very promising, as the PCP schedules exhibit good stability and improved average execution time (14 percent on average, up to 30 percent versus FPS and up to 40 percent versus the FIFO scheduler).

On Implementation of Software Acoustic Cancellation

The implementation of a software acoustic echo canceller (AEC) on personal computers (PC) is much more difficult than just migration of the well defined algorithms. Software AECs have to deal with the diverse hardware environments, which are usually low-cost and inaccurate, and the software environment, which generally is committed to sharing resources through multi-tasking yet providing no real-time guarantees. Hardware differences lead to sampling rate differences and echo path nonlinearity, while the software environment can cause discontinuity of the audio stream. In this paper, these factors are investigated, and addressed by improved software AEC based on the coloration effect filter algorithm.

Distributed Real-Time Protocols for Industrial Control Systems: Framework and Examples

The automation of today's large-scale industrial systems relies on the operation of distributed controller devices that perform local computations and exchange information via communication networks. The subject of this paper is the development of a family of shared-medium industrial communication protocols that support the transmission of real-time (RT) and nonreal-time (nRT) data among distributed controller devices. Different from existing protocols, we suggest to incorporate information that is available from the control application in the protocol definition. As a result, our protocols dynamically change the bandwidth allocation on the shared medium according to the instantaneous communication requirements while ensuring hard RT guarantees. Following the recent developments in industrial automation, our protocols can be realized as software layers on top of low-cost conventional Ethernet.

Efficient real-time divisible load scheduling

Providing QoS and performance guarantees to arbitrarily divisible loads has become a significant problem for many cluster-based research computing facilities. While progress is being made in scheduling arbitrarily divisible loads, current approaches are not efficient and do not scale well. In this paper, we propose a linear algorithm for real-time divisible load scheduling. Unlike existing approaches, the new algorithm relaxes the tight coupling between the task admission controller and the task dispatcher. By eliminating the need to generate exact schedules in the admission controller, the algorithm avoids high overheads. We also proposed a hybrid algorithm that combines the best of our efficient algorithm and a previously best-known approach. We experimentally evaluate the new algorithm. Simulation results demonstrate that the algorithm scales well, can schedule large numbers of tasks efficiently, and performs similarly to existing approaches in terms of providing real-time guarantees.

Fidelity-Aware Utilization Control for Cyber-Physical Surveillance Systems

Recent years have seen the growing deployments of Cyber-Physical Systems (CPSs) in many mission-critical applications such as security, civil infrastructure, and transportation. These applications often impose stringent requirements on system sensing fidelity and timeliness. However, existing approaches treat these two concerns in isolation and hence are not suitable for CPSs where system fidelity and timeliness are dependent on each other because of the tight integration of computational and physical resources. In this paper, we propose a holistic approach called Fidelity-Aware Utilization Controller (FAUC) for Wireless Cyber-physical Surveillance (WCS) systems that combine low-end sensors with cameras for large-scale ad hoc surveillance in unplanned environments. By integrating data fusion with feedback control, FAUC can enforce a CPU utilization upper bound to ensure the system's real-time schedulability although CPU workloads vary significantly at runtime because of stochastic detection results. At the same time, FAUC optimizes system fidelity and adjusts the control objective of CPU utilization adaptively in the presence of variations of target/noise characteristics. We have implemented FAUC on a small-scale WCS testbed consisting of TelosB/Iris motes and cameras. Moreover, we conduct extensive simulations based on real acoustic data traces collected in a vehicle surveillance experiment. The testbed experiments and the trace-driven simulations show that FAUC can achieve robust fidelity and real-time guarantees in dynamic environments.

An experimental evaluation of the scalability of real-time scheduling algorithms on large-scale multicore platforms

We present an experimental analysis of the scalability of 13 multicore real-time scheduling algorithms on a 48-core AMD platform. The algorithms include G-EDF, P-EDF, C-EDF, and G-NP-EDF. Comparisons are made based on schedulability and tardiness. The algorithms are implemented in a real-time Linux kernel we create called ChronOS. ChronOS extends the Linux kernel's &lt;tt&gt;PREEMPT_RT&lt;/tt&gt; patch with a flexible, scalable real-time scheduling framework. Our study shows that it is possible to implement global fixed and dynamic priority real-time scheduling algorithms which will scale to large-scale multicore platforms. Interestingly, and in contrast to the conclusions of prior research, our results reveal that some global scheduling algorithms (e.g., G-NP-EDF) are scalable on 48-core machines. In our implementation, scalability is restricted by lock contention over the global schedule and the cost of interprocessor communication, rather than the global task queue implementation. We show that algorithms implemented with scalability as a first-order goal are able to provide real-time guarantees on our 48-core platform.