System performance evaluation by combining RTC and VHDL simulation: A case study on NICs

Abstract

• We combine Real-Time Calculus (RTC) and VHDL simulation for performance evaluation. • We predict analytically NIC’s buffer-size requirements in a network node. • We identify FIFO overflow scenarios by analytic methods. • We present a compositional model of the network-to-memory data path using RTC. • We provide real-time guarantees that are valid up to a certain level of confidence. Analytic models allow the performance evaluation of proposed system changes without requiring complex and expensive detailed simulations. In this paper, Real-Time Calculus (RTC), a high-level analysis technique previously proposed for stream-processing hard real-time systems and frequently used to evaluate trade-offs in packet stream processing architectures, has been applied to analyse the behaviour of network interfaces. Moreover, the simulation of HDL (Hardware Description Language) models has been used to build the RTC descriptions required to analyse the behaviour of these relatively complex systems. As a case study of this proposed combination of Real-Time Calculus and HDL simulation, the prediction of buffer-size requirements and bottlenecks on the Network Interface Card (NIC) of a node receiving Ethernet packets, is also provided. This work intends to increase the efficiency of the performance evaluation of systems by providing real-time guarantees on delays and backlogs that are valid up to a certain level of confidence, as opposed to the hard guarantees commonly derived by formal methods.