Real-time Field Programmable Gate Array Research Articles

Real-time low-complexity automatic modulation classifier for pulsed radar signals

An automatic modulation classifier (AMC) based on low-complexity signal features and a hierarchical decision tree is presented for pulsed radar applications. This AMC is implemented on a field-programmable gate array (FPGA) platform. The algorithm has been designed to minimize the computational burden to achieve real-time operation. The novelty of the paper consists of the development of a low-computational-complexity radar AMC suitable for real-time FPGA implementation.

Efficient Estimation and Pilot-Free Online Re-Calibration of $I/Q$ Imbalance in Broadband Direct-Conversion Transmitters

This paper proposes an efficient estimation and pilot-free online re-calibration scheme for frequency-selective I/Q imbalance in broadband direct-conversion transmitters (Txs) with multi-band multi-standard capability. For such Txs, the main challenge lies in the online re-calibration during normal operation, where an ordinary Tx signal, instead of dedicated pilot signals, is used for estimation. In particular, it can happen that the Tx signal consists of noncontiguous subbands and has large spectral gaps, which will cause a severe ill-conditioned matrix problem in existing state-of-the-art (SoA) schemes deploying least squares (LS) estimation. In the proposed scheme, this problem is avoided by exploiting the fact that the frequency-selective part of I/Q imbalance is approximately time invariant. Therefore, before normal operation, pilot-based initial estimation is carried out to achieve high-precision estimation of the frequency-selective part. Afterward, pilot-free online re-calibration is applied to cope with the time-varying frequency-independent part. Both theoretical analysis and numerical simulations show that the proposed re-calibration scheme is well conditioned and clearly outperforms the existing SoA schemes deploying LSE. To emphasize practical deployments, we also conduct performance analysis considering time synchronization error (TSE) and provide a Toeplitz-extension-based solution to make the scheme robust against TSE. We further provide complexity analysis and show that the proposed scheme has much lower complexity than the SoA schemes. Finally, the performance of the proposed scheme and the fundamental working assumptions are verified by both numerical simulations and hardware-in-the-loop (HIL) experiments with real radio-frequency signal measurements, including real-time field-programmable gate-array (FPGA) implementation of the developed digital calibration circuits.

Real-time distortion correction of fish-eye lens based on Bayer image signal

The imaging system based on a fish-eye lens generally has to correct the distortion of fish-eye images. The distortion correction based on the Bayer image signal is valuable, such as reducing the computation burden of image signal processing chips and providing a new imaging system structure of fish-eye lens. In this paper, a distortion correction method of fish-eye lens based on the Bayer image signal is proposed. Firstly, a distortion correction method that focuses on vertical straight lines and processing delay is proposed. Secondly, according to the correlation among color channels of the Bayer image, a novel Hermite interpolation method appropriate for Bayer image signal is proposed. Finally, a prototype system of fish-eye-lens-based imaging is established and the real-time field-programmable gate array (FPGA) implementation of the proposed method is demonstrated. The experiment demonstrates that the proposed distortion correction is not only characteristic of real-time processing and the smaller computation amount, but also applicable to embedded hardware.

Easily implementable field programmable gate array-based adaptive optics system with state-space multichannel control

In this paper, an easily implementable adaptive optics system (AOS) based on a real-time field programmable gate array (FPGA) platform with state-space multichannel control programmed by LabVIEW has been developed, and also integrated into a laser focusing system successfully. To meet the requirements of simple programming configuration and easy integration with other devices, the FPGA-based AOS introduces a standard operation procedure including AOS identification, computation, and operation. The overall system with a 32-channel driving signal for a deformable mirror (DM) as input and a Zernike polynomial via a lab-made Shack-Hartmann wavefront sensor (SHWS) as output is optimally identified to construct a multichannel state-space model off-line. In real-time operation, the FPGA platform first calculates the Zernike polynomial of the optical wavefront measured from the SHWS as the feedback signal. Then, a state-space multichannel controller according to the feedback signal and the identified model is designed and implemented in the FPGA to drive the DM for phase distortion compensation. The current FPGA-based AOS is capable of suppressing low-frequency thermal disturbances with a steady-state phase error of less than 0.1 π within less than 10 time steps when the control loop is operated at a frequency of 30 Hz.

Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder

Motion estimation is the most computationally intensive part of video encoders, as the compression efficiency usually increases with the amount of computations. The adaptive computationally scalable motion-estimation algorithm and its hardware implementation described in this paper allow the H.264/AVC encoders to achieve efficiencies close to optimal in real-time conditions. The algorithm employs several search strategies to adapt to local motion activity, and the number of checked search points is set by the encoder controller for each macroblock. The algorithm can achieve results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies over time. The architecture applies a novel dataflow. First, the motion vector generation is not constrained by the calculation of residuals and corresponding costs. Second, the fractional-pel interpolation is performed prior to the integer-pel search. Third, the ME and compensation use the same resources. The architecture is verified in the real-time field-programmable gate array hardware encoder. The synthesis results and the real-time verification show that the design can support HDTV at 200 MHz for 0.13-μm TSMC technology.

Efficient Bayesian Tracking of Multiple Sources of Neural Activity: Algorithms and Real-Time FPGA Implementation

We propose new Bayesian algorithms to automatically track current dipole sources of neural activity in real time. We integrate multiple particle filters to track the dynamic parameters of a known number of dipole sources, resulting in reducing the computational intensity incurred due to the large number of sensors required to observe magnetoencephalography (MEG) or electroencephalography (EEG) measurements. When we also need to estimate the time-varying number of dipole sources, we develop an algorithm based on applying probability hypothesis density filtering (PHDF) for multiple object tracking. The PHDF is implemented using particle filters (PF-PHDF), and it is applied in a closed-loop with MEG/EEG measurements to first estimate the number of sources and then their corresponding amplitude, location and orientation. The PF-PHDF tracking algorithm uses an online, window-based multiple channel decomposition processing approach that reduces the overall processing time and computational complexity. We demonstrate the improved performances of the proposed algorithms by simulating neural activity tracking systems witWe propose new Bayesian algorithms to automatically track current dipole sources of neural activity in real time. We integrate multiple particle filters to track the dynamic parameters of a known number of dipole sources, resulting in reducing the computational intensity incurred due to the large number of sensors required to observe magnetoencephalography (MEG) or electroencephalography (EEG) measurements. When we also need to estimate the time-varying number of dipole sources, we develop an algorithm based on applying probability hypothesis density filtering (PHDF) for multiple object tracking. The PHDF is implemented using particle filters (PF-PHDF), and it is applied in a closed-loop with MEG/EEG measurements to first estimate the number of sources and then their corresponding amplitude, location and orientation. The PF-PHDF tracking algorithm uses an online, window-based multiple channel decomposition processing approach that reduces the overall processing time and computational complexity. We demonstrate the improved performances of the proposed algorithms by simulating neural activity tracking systems with both synthetic and real data. We map the proposed algorithms onto Xilinx Virtex-5 field-programmable gate array (FPGA) platforms and demonstrate real-time tracking performance. For example, our results showed that the PF-PHDF algorithm can process 100 data samples from three dipoles in only 5.1 ms, when 3 dipole sources are present.h both synthetic and real data. We map the proposed algorithms onto Xilinx Virtex-5 field-programmable gate array (FPGA) platforms and demonstrate real-time tracking performance. For example, our results showed that the PF-PHDF algorithm can process 100 data samples from three dipoles in only 5.1 ms, when 3 dipole sources are present.

Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL

Neurons are complex biological entities which form the basis of nervous systems. Insight can be gained into neuron behavior through the use of computer models and as a result many such models have been developed. However, there exists a trade-off between biological accuracy and simulation time with the most realistic results requiring extensive computation. To address this issue, a novel approach is described in this paper that allows complex models of real biological systems to be simulated at a speed greater than real time and with excellent accuracy. The approach is based on a specially developed neuron model VHDL library which allows complex neuron systems to be implemented on field programmable gate array (FPGA) hardware. The locomotion system of the nematode Caenorhabditis elegans is used as a case study and the measured results show that the real time FPGA based implementation performs 288 times faster than traditional ModelSim simulations for the same accuracy.

Real-Time FPGA Processing for High-Speed Optical Frequency Domain Imaging

We present a novel algorithm for reconstructing interferograms acquired in optical frequency domain imaging (OFDI). The algorithm was developed specifically for processing in field programmable gate arrays (FPGAs) and featured the use of a finite-impulse-response (FIR) filter implementation of B-spline interpolation for efficiently re-sampling k-space. When implemented in FPGAs, the algorithm allowed for real-time processing of interferograms acquired with a high-speed OFDI system at 54 kHz and a sampling rate of 100 MS/s.

Nuclear Medical Image Treatment System Based On FPGA in Real Time

We present in this paper an acquisition and treatment system designed for semi-analog Gamma-camera. It consists of a nuclear medical Image Acquisition, Treatment and Display chain (IATD) ensuring the acquisition, the treatment of the signals (resulting from the Gamma-camera detection head) and the scintigraphic image construction in real time. This chain is composed by an analog treatment board and a digital treatment board. We describe the designed systems and the digital treatment algorithms in which we have improved the performance and the flexibility. The digital treatment algorithms are implemented in a specific reprogrammable circuit FPGA (Field Programmable Gate Array).

Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation

The paper describes the implementation of a novel Analog-to-Digital-Converter (ADC) test technique for next generation low cost massive parallel ADC testing using a Field Programmable Gate Array (FPGA) on tester load board. The goal is to test the ADC which is embedded in an automotive micro controller with only pure digital tester sources. Therefore, the analog test stimulus for the ADC is generated by using ??-modulation technique off-line and analog filtering on load board. The digital test response is analyzed by a FPGA in real time by comparing the measured data with a reference signal. The modular concept of FPGA evaluation allows for quick and flexible reaction on changing production test requirements. Simply by reprogramming the FPGA with a new module there is no need of any hardware reconfigurations. Measurements with a high precision reference ADC in laboratory environment show that the method is ready for production.

Real-time face detection and lip feature extraction using field-programmable gate arrays

This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model's size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6% correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15050 logic cells, or about six times less than a current comparable FPGA face detection system.

2-D multirate algorithms for efficient implementation of edge detection

Edge detection is a fundamental issue in image analysis. This paper proposes multirate algorithms for efficient implementation of edge detector, and a design example is illustrated. The multirate (decimation and/or interpolation) signal processing algorithms can achieve considerable savings in computation and storage. The proposed algorithms result in mapping relations of their z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase decomposition counterparts. The mapping properties can be readily utilized to efficiently analyze and synthesize multirate edge detection filters. The Very high-speed Hardware Description Language (VHDL) simulation results verify efficiency of the algorithms for real-time Field Programmable Gate-Array (FPGA) implementation.

Real-time field programmable gate array architecture for computer vision

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to mini- mize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to im- prove its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very-large-scale-integrated de- vices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed. © 2001