Real Circuit Operation Research Articles

Gate Current in p-GaN Gate HEMTs as a Channel Temperature Sensitive Parameter: A Comparative Study between Schottky- and Ohmic-Gate GaN HEMTs

In this work, a comparison between the gate-driving requirements of p-GaN HEMTs with gate contact of Schottky and Ohmic type is presented. Furthermore, the presence of a gate current of different magnitude is experimentally verified for both types of devices. Successively, the possibility of using the gate current as a temperature-sensitive parameter and its monitoring during real circuit operation is proposed. The viability of monitoring the gate current without introducing additional complexity in the gate driver is examined through experimental measurements on commercially available p-GaN HEMTs.

NBTI: Experimental investigation, physical modelling, circuit aging simulations and verification

For more than 10years a major part of MOSFET reliability publications are dealing with (N)BTI. The degradation and recovery mechanism is still not fully understood (Grasser, 2014). New publications demonstrate incessantly the agile debate on this important transistor aging phenomenon.In this paper we want to illuminate four important subareas for the understanding of NBTI. First, we will discuss experimental investigations. Depending on the pursued goal of the measurements different set-ups are required to gain the desired information. To get meaningful statements regarding the median NBTI degradation of MOSFET with a relatively small number of test devices, e.g. for regular lifetime predictions, DUTs with larger active area are used. The relatively high number of defects within one transistor delivers stable (averaged) parameter shifts with a small number of DUTs. Relatively small area devices are the best choice to investigate the physical nature of the degradation and recovery mechanisms. The small number of defects within those devices enables to obtain and investigate the trapping and de-trapping of single charges. To investigate the NBTI impact on the parameter variability array structures with a higher number of devices under test (DUTs) are appropriate. The very fast and strong recovery behavior of NBTI has to be considered for the test structure design and for the measurement set-up.Based on the measurement results and gained knowledge we can refine the modelling of the degradation and recovery mechanism. We could improve the understanding of the temperature dependence and utilize this knowledge to reduce measurement efforts for model calibration for a circuit aging simulator (Pobegen and Grasser, 2013). An adequately accurate model at a manageable effort for characterization and implementation is a key factor for a successful integration of an aging simulator in the design flow. A correct modelling of the parameter recovery during circuit function is especially challenging.The last chapter introduces a new method to verify the NBTI model and the correct implementation into a circuit aging simulator with real hardware measurements. An arbitrary waveform generator is used to drive single transistors in identical operation modes with identical sequence and proportion of each single operating point as during real circuit operation. In this manner, the calculated drift for one transistor in a circuit can be compared with a measurement drift for a given stress pattern.

Compact Modeling of Statistical BTI Under Trapping/Detrapping

The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (t <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and dynamic voltage scaling (DVS) in real circuit operation. To overcome these barriers, this paper: 1) practically explains the aging statistics due to randomness in number of traps with the log(t) model, accurately predicting the mean and variance shift; 2) proposes cycle-to-cycle model (from the first principles of trapping) to handle aging under multiple supply voltages, predicting the nonmonotonic behavior under DVS; 3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles; and 4) comprehensively validates the new set of aging models with 65-nm statistical silicon data. Compared with previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard banding during the design stage.

Impact of static and dynamic stress on threshold voltage instability in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors

This letter investigates the impact of static and dynamic stress on threshold voltage (Vth) instability in ultrathin n-channel metal-oxide-semiconductor field-effect transistors with hafnium-based gate stacks. Experimental results indicate Vth shift under dynamic stress is more serious than that under static stress due to charge trapping within the high-k dielectric. Capacitance-voltage techniques demonstrated that electron trapping under dynamic stress was located in the high-k dielectric near the source/drain overlap region rather than throughout the overall dielectric layer. This implies in real circuit operation, the phenomenon of electrons trapped in high-k near the source/drain overlap is the main issue affecting Vth instability.

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative-bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (<formula formulatype="inline"><tex>$V_{t}$</tex></formula>) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent <formula formulatype="inline"><tex>$V_{t}$</tex></formula> degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based <formula formulatype="inline"><tex>$V_{t}$</tex></formula> model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: 1) static noise margin; 2) statistical <emphasis emphasistype="smcaps">read</emphasis> and <emphasis emphasistype="smcaps"> write</emphasis> stability; 3) parametric yield; and 4) standby leakage current <formula formulatype="inline"><tex> $(I_{\rm DDQ})$</tex></formula>. We show that due to NBTI, <emphasis emphasistype="smcaps">read</emphasis> stability of SRAM cell degrades, while <emphasis emphasistype="smcaps">write</emphasis> stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation. </para>

Reliability simulation of AC hot carrier degradation for deep sub‐micron MOSFETs

AbstractHigh performance under low supply voltage is required for ULSIs in combination with the higher packing density that results from scaling down to the deep sub‐micron region. For this requirement, the conventional method, using the DC hot carrier lifetime of MOSFETs as measured by DC stress, overestimates the degradation caused by real circuit operation. As a result, the improvement of MOSFET performance is limited by attempting to satisfy the overestimated hot carrier criteria under DC stress. Therefore, it is strongly desired that the reliability simulation estimate accurately hot carrier degradation in real circuit operation. We have found that the degradation rate depends on the stress conditions and can be expressed in terms of the difference between the gate and drain voltages. Hence, in this paper, we propose a new method of modeling and calculation of hot carrier degradation that incorporates this dependence and will demonstrate improved accuracy in predicting degradation and life time for both AC and DC bias conditions. We also propose a new duty ratio extraction method that can be used to predict the lifetime for hot carrier degradation under actual circuit operation.