Voltage Readout Research Articles

Novel NAND DRAM with surrounding gate transistor (SGT)‐type gain cell

AbstractA novel NAND DRAM with SGT‐type gain cell is proposed. This SGT‐type gain cell structure is composed of an SGT and SGT‐type capacitor stacked vertically on a planar read transistor. Its cell size can be reduced to 4F2 since it can be arranged to have the cross‐point configuration. Therefore, high‐density DRAM is achieved. Since it operates as a gain cell, it is possible to obtain sufficient signal charge regardless of the stored amount. Therefore, the proposed DRAM operates at low supply voltages, where it is difficult to obtain sufficient read‐out voltage in conventional DRAM. It is shown that the novel NAND DRAM with SGT‐type gain cell achieves high‐density and low‐voltage operation. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(7): 1–8, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10198

Two terminal large area single and double p-i-n devices for image and color recognition

ABSTRACTLarge area hydrogenated amorphous silicon single and stacked p-i-n structures with low conductivity doped layers are proposed as monochrome and color image sensors. All have the same intrinsic layer and in the doped layers the resistivity and optical gap was controlled through the addition of methane to the doping gas. The current-voltage characteristics and the spectral sensitivity under different illumination conditions are analyzed. The sensor output characteristics are evaluated under different read-out voltages and scanner wavelengths. To extract information on image range, intensity and color, a modulated light beam scans the sensor active area at three appropriate bias voltages and the photoresponse in each scanning position (“sub-pixel”) is recorded. The investigation of the sensor output under different scanner wavelengths and varying electrical bias reveals that the response can be tuned, thus enabling color separation. The operation of the sensor is exemplified and supported by a numerical simulation.

A spherical gravitational wave detector readout by nearly quantum limited SQUIDs

We are developing nearly quantum limited two-stage SQUID systems for the readout of the MiniGRAIL, the first spherical gravitational wave detector with a diameter of 65 cm and a mass of 1150 kg. The two-stage SQUID systems are based on a conventional dc SQUID as the sensor and a double relaxation oscillation SQUID (DROS) as the second stage. The SQUID systems will be coupled to the detector via a multi-mode inductive transducer. The large flux-to-voltage transfer of the two-stage SQUID system allows a direct voltage readout scheme, i.e. without (ac flux) modulation. At T = 4.2 K, the energy resolution in flux-locked loop was measured to be ε = 27 h, and at a temperature around 20 mK, the energy resolution is expected to reach the quantum limit.

Drift and Hysteresis Effects on AlN/SiO2 Gate pH Ion-Sensitive Field-Effect Transistor

The nonideal and unstable factors of AlN-based ion-sensitive field-effect transistor (ISFET) devices including the drift and hysteresis effects have been investigated in this study. The drift and hysteresis of AlN-based pH-ISFET devices have been measured using a constant current constant voltage (CCCV) readout circuit. The drift rates were obtained by long-time monitoring for 12 h in pH = 1, 3, 5, 7, 9, and 11 buffer solutions, which indicated that the drift rate increased with the pH value. The hysteresis effect was investigated by exposing the AlN gate ISFET in pH = 7–3–7–11–7 loop cycles with loop times of 960 s, 1920 s and 3840 s, and the magnitudes of hysteresis of 1.0, 1.5 and 4.5 mV were obtained, respectively. The temperature coefficient of hysteresis was found to be approximately 0.234 mV/°C. In addition, it was also found that the hysteresis width with pH started from acid side is smaller than that started from basic side, which results in an asymmetric hysteresis effect.

Bitline GND sensing technique for low-voltage operation FeRAM

In this sensing technique, pMOS charge transfer maintains the bitline level near the GND when the plate line goes high. It gives 0.5-V higher readout voltages across the cell capacitors and enables a 0.4-V higher differential amplitude in a 512-cell per bitline structure compared with the conventional high-impedance bitline sensing technique. Using the shifted bias plate line layout, only eight cells and eight sense amplifiers per cell mat are activated, and simulations show 8.06 mW at 3 V and 5 MHz, which is about the same power consumption as the conventional device.

Low-noise SQUIDs with large transfer: two-stage SQUIDs based on DROSs

We have realized a two-stage integrated superconducting quantum interference device (SQUID) system with a closed loop bandwidth of 2.5 MHz, operated in a direct voltage readout mode. The corresponding flux slew rate was 1.3×10 5 Φ 0/s and the measured white flux noise was 1.3 μ Φ 0/√Hz at 4.2 K. The system is based on a conventional dc SQUID with a double relaxation oscillation SQUID (DROS) as the second stage. Because of the large flux-to-voltage transfer, the sensitivity of the system is completely determined by the sensor SQUID and not by the DROS or the room-temperature preamplifier. Decreasing the Josephson junction area enables a further improvement of the sensitivity of the two-stage SQUID systems.

A 1.8-V ΔΣ modulator interface for an electret microphone with on-chip reference

The design of a delta-sigma ( ) analog-to-digital converter (ADC) for direct voltage readout of an electret micro- phone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged to- gether with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth- order ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumen- tation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A com- bined continuous-time/switched-capacitor design is used to mini- mize power consumption. Index Terms—Analog-to-digital conversion, CMOS analog IC, continuous time, delta-sigma modulator, electret micro- phone, high input impedance, low-voltage bandgap reference, single-ended input, switched capacitor.

Multi-loop relaxation oscillation SQUID magnetometers with large flux-to-voltage transfer functions

A multi-loop Relaxation Oscillation SQUID (ROS) with direct voltage readout is fabricated and characterized. We designed and fabricated four-loop ROSs with the size of 5 mm /spl times/5 mm. A maximum voltage modulation of 100 /spl mu/V and a flux-to-voltage transfer function of more than 10 mV//spl Phi//sub 0/ were obtained. With a direct voltage readout flux locked loop (FLL), a magnetic field resolution of 4 to 10 fT//spl radic/Hz was obtained in the frequency range from 0.3 Hz up to the white region. Using this magnetometer, we demonstrated the measurement of a brain response.

Deglitching methods by the ISOPHOT Interactive Analysis (PIA)

The ISOPHOT detectors were continuously exposed to high energy cosmic particles hits, resulting in an average hit rate frequency of an event per every 7 s. The net effect is a disturbance of the readout voltages, which decreases the signal-to-noise ratio and hence the photometric accuracy level. Thanks to the highly redundant readout method of ISOPHOT it is relatively easy to identify cosmic particle hits which have enough energy to produce a noticeable deviation in the readouts. The most energetic particles can cause a short term change in the detector response. Different algorithms are implemented into PIA to cope with this problem. PIA provides handy interfaces to perform individual treatment of the data and optimize the parameters of the deglitching algorithms.

Two-stage amplifier based on a double relaxation oscillation superconducting quantum interference device

A low-noise single-chip two-stage superconducting quantum interference device (SQUID) system with a double relaxation oscillation SQUID as the second stage has been realized. The system was operated in a direct voltage readout mode, with a closed loop bandwidth up to 1 MHz. Operated at 4.2 K, the white flux noise measured in flux locked loop was 1.3 μΦ0/√Hz, corresponding to an energy sensitivity of ε≈27h. Owing to the large flux-to-voltage transfer of up to 3.6 mV/Φ0, the room-temperature preamplifier noise did not dominate the overall flux noise.

HTS SFQ T-flip flop with directly coupled readout

The authors report the design, fabrication, and test results of single flux quantum (SFQ) toggle flip flop circuits. These circuits, investigated as building blocks of an HTS counting ADC, feature a directly coupled readout junction stack similar to those used in LTS RSFQ circuits. The directly coupled circuit delivers higher readout voltage, hence potentially higher operating speed than magnetically coupled alternatives. The circuits were fabricated using two multilayer HTS SNS junction integrated circuit technologies (one at Northrop Grumman and the other at TRW) featuring three YBCO depositions. Initial testing demonstrated toggling of a T-flip flop in response to SFQ pulses generated by integrated dc/SFQ converters. The readout voltage is shown to approach 40% of the junction I/sub C/R/sub N/ product, and as high as 100 /spl mu/V at 65K. Test results are compared with predicted fabrication process parameter requirements. To increase margins and tolerance to process parameter variations, improvements to the design have been made using JSpice and MALT.

Multilayer HTS SFQ analog-to-digital converters

We have fabricated and measured high T/sub c/ superconductor single flux quantum 1-bit flux-counting analog-to-digital converters (ADCs). The ADCs were made with a multilayer all-epitaxial process which incorporates 10 edge SNS (superconductor-normal-superconductor) or step-edge grain boundary (SEGB) Josephson junctions with a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// groundplane. The ADC consists of a quantizer connected to a Toggle flip-flop through a buffer-like stage. Direct readout of the flux state of the T flip-flop was made with a Read SQUID inductively coupled through a hole in the groundplane. The circuits were operated at 65 K and low speeds. The SNS circuits outperformed the SEGB circuits because of their higher readout voltages and tighter critical current spreads.

Experimental study of the spatially-modulated light detector

Usually, integrated detectors in CMOS exhibit long recovery times, limiting the detector bandwidth to only a few MHz. This is due to the long absorption length and the slow diffusion speed of photo-generated carriers. Different approaches have been proposed to solve these problems hereby taxing the compatibility with standard CMOS fabrication processing. We present a novel detector for high-speed light detection in standard CMOS. To solve the problem of slow CMOS-detector recovery, the incident light is spatially modulated and the spatially modulated component of the photo-generated carrier distribution is measured. Though only a single light input signal is required, from the detector on, analog signal processing can be achieved fully differentially. Subsequently, expected good PSRR (Power supply rejection ratio) allows integration with digital circuits. Avoiding hybridization eliminates the conventional problems caused by bonding-pad capacitance, bonding-wire inductance. This reduces the associated signal degradation. In addition, the very low detector capacitance, due to the low effectively used detector area and the low area capacitance of the n-well junction, yields high voltage readout of the detector. This facilitates further amplification and conversion to digital signal levels. The detector will be applicable in arrays due to expected low cross talk. The expected fields of operation involve: serial and parallel optical communication receivers (e.g. for WDM), DVD-reading heads with integrated amplifier, etc. First measurements show 200 Mbit/s operation with a detector-responsivity of 0.05 A/W at λ=860 nm and 0.132 A/W at λ=635 nm. The detector has inherently a low capacitance, in this case only 50 fF (for an effective detector area of 70×70 μm 2).

Double relaxation oscillation superconducting quantum interference devices with gradiometric layout

Double relaxation oscillation superconducting quantum interference devices (DROSs) with a gradiometric signal SQUID and either a reference SQUID or a reference junction will be presented in this article. The devices are user friendly, particularly those with a reference junction. Because of the large flux-to-voltage transfer of ∂V/∂Φ=0.7–1 mV/Φ0, the devices can be operated in a flux locked loop based on direct voltage readout without loss of sensitivity. The typical white flux noise of the DROSs amounts to √SΦ=5–6μΦ0/√Hz, which corresponds to an energy resolution ε=SΦ/2Lsq≃200 h. Coupled to an external planar first-order gradiometer, a white magnetic field sensitivity of √SB<2 fT/√Hz was measured inside a magnetically shielded room.

Writing transition noise due to random particle distribution in thin recording media

Fluctuations in the magnetization transition due to random distribution of position, particle size, anisotropy and misorientation of easy axis of a system of thermally activated noninteracting single domain particles (SDPs) in recording media under a recording head field has been analyzed, and the corresponding variance examined, by Monte Carlo simulation. Larger values of the thermal factor Kv p/ k B T give rise to steeper magnetization hysteresis curves, narrower transition widths and, correspondingly, sharper and narrower noise distributions. Heterogeneous media with an admixture of several different particle size distributions lead to a wider transition width at a lower noise level. Random anisotropy constant distribution imparts a far more severe effect to broaden the transition width while keeping the variance wider and shallower than that due to random particle size distribution. Similarly, random in-plane misorientation distribution of the easy axis is much less effective to broaden the transition width than that due to the out-of-plane misorientation. Variance in the read-out voltage becomes asymmetric when the head gap length is comparable to the transition width.

Multilayer HTS SFQ analog-to-digital converters

We have fabricated and measured high T/sub c/ superconductor single flux quantum 1-bit flux-counting analog-to-digital converters (ADCs). The ADCs were made with a multilayer all-epitaxial process which incorporates 10 edge SNS (superconductor-normal-superconductor) or step-edge grain boundary (SEGB) Josephson junctions with a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// groundplane. The ADC consists of a quantizer connected to a Toggle flip-flop through a buffer-like stage. Direct readout of the flux state of the T flip-flop was made with a Read SQUID inductively coupled through a hole in the groundplane. The circuits were operated at 65 K and low speeds. The SNS circuits outperformed the SEGB circuits because of their higher readout voltages and tighter critical current spreads.

Device design with automatic simulation system for basic CCD characteristics

A simulation system has been developed to automatically analyze basic electrical characteristics of a charge-coupled device (CCD) image sensor from a process simulation result. This system shortened the simulation period to approximately 1/10 by getting rid of complicated repetitious procedures. A high-performance new cell technology has been developed successfully with improving impurity distribution in shorter development time by using this system. This technology has been realized as a CCD cell pixel with CCD charge quantity of 1.8 times, effective transfer efficiency of over 99%, no image lag for driving read-out pulse voltage in comparison with conventional technology. A 1/4-in 330 K square pixel progressive-scan CCD was fabricated with this technology. These results are described to demonstrate the effectiveness of the automatic simulation system.

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V/sub cc/ bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%.

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.

Multichannel SQUID magnetometry using double relaxation oscillation SQUID's

A highly sensitive first-order gradiometer based on double relaxation oscillation SQUID's (DROS's) for multichannel use is presented. The white flux noise level of the bare DROS's is 4.5 /spl mu//spl Phi//sub 0///spl radic/Hz (/spl epsi/=275 h). With wire-wound first-order gradiometers, having a baseline of 40 mm, the white magnetic field noise equals 4 fT//spl radic/Hz. As a result of the high flux-to-voltage transfer of the DROS's of about 1 mV//spl Phi//sub 0/, this low noise level could be obtained with simple room-temperature flux locked loop electronics based on direct voltage readout. The relaxation frequency of the present DROS's is approximately 1 GHz. No degradation of the DROS characteristics caused by interference between relaxation oscillations in two adjacent channels has been observed, although the gradiometers are spaced by less than 1 mm. This shows that DROS's can be used in multichannel SQUID magnetometers.