Readout Circuit Architecture Research Articles

Low-power and cost-effective readout circuit design for compact semiconductor gas sensor systems

This study introduces a novel readout circuit architecture that enhances semiconductor gas sensor systems by reducing power consumption, enabling miniaturization, and improving economic viability. Validated at the PCB level, the design shows strong commercial potential by addressing power efficiency and signal accuracy challenges. The technology is adaptable for applications in environmental monitoring, industrial safety, and medical diagnostics, where efficient and reliable gas sensing is essential.

Mask configurable readout circuit architecture for an ultra-high-resolution CMOS image sensor: publisher's note.

This publisher's note reports a correction in Appl. Opt.61, 2565 (2022)APOPAI0003-693510.1364/AO.453904.

Mask configurable readout circuit architecture for an ultra-high-resolution CMOS image sensor.

As the level of detail in today's images increases, so does the demand for resolution. Due to the necessity of mask stitching technology for full exposure of large array chips, we propose a mask configurable readout circuit architecture, which is suitable for large array structures. However, the stitchable readout circuit architecture has some non-ideal effects: row driver function failure and the column non-consistency problem. In our design, we solve the problem of column non-consistency after stitching. At the same time, we changed the signal transmission structure in order to avoid the row driver function failure caused by the mask stitching. In this paper, a prototype 2130×2130 CMOS image sensor is fabricated in 0.11 µm CMOS technology. The chip can capture images at 20 fps and reduce fixed pattern noise (FPN) from 3.5% to 1.5% through correction techniques. The architecture proposed in this paper is suitable for large array image sensors.

Design and initial characterization of MIC4, the monolithic active pixel sensor prototype for CEPC vertex detector

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs factory to produce adequate events, which are the basis for high-precision measurements of the Higgs boson. The vertex detector in the CEPC should meet the requirements of a low material budget, high spatial resolution, fast readout speed and low power consumption. A monolithic active pixel sensor (MAPS) has been selected as the most promising technology for the vertex detector. The MIC4 sensor is the first prototype developed within the preliminary R&D activities of the CEPC vertex detector. It has been implemented in the TowerJazz 180 nm CMOS image sensor (CIS) process. It measures 3.1 mm × 4.6 mm and features a 128 row × 64 column pixel array with a pixel pitch of 25μm. In this work, a binary front-end has been designed for a compact pixel combined with a sparsified readout circuitry. Each pixel is composed of an amplifier, a shaper, a discriminator and digital logic. A new asynchronous zero-suppression data-driven readout circuit architecture is proposed and implemented in MIC4. We have performed some initial tests on this chip and obtained detailed results. The front-end features a peaking time below 1μs, a shaping time less than 3μs, a charge threshold of approximately 100 e−, an average temporal noise (TN) of 6 e− and a fixed pattern noise (FPN) of 36 e−. The addresses of the fired pixels can be readout in the digital part of the chip at a clock running at 30 MHz with the new data-driven readout circuit architecture. The hit map under 55Fe X-ray exposure shows that the sensor designed in MIC4 works well. The probability of single event latch-up (SEL) σSEL is 1.02 × 10−6 cm2 at a linear energy transfer (LET) of 20.05 MeV cm2/mg.

Ultracompact Microwatt CMOS Current Readout With Picoampere Noise and Kilohertz Bandwidth for Biosensor Arrays.

High-density on-chip electrochemical biosensor arrays are advancing toward a crucial role in health monitoring and development of new medicines and medical treatments. Nanopore and ion channel based sensors especially have great potential but present demanding resolution/speed/power/area requirements on instrumentation circuits. This paper presents a pixel-level current readout circuit and new group-cluster architecture to address the circuit challenges in high-performance biosensor arrays. Fabricated in 0.5 μm CMOS, this electrochemical voltammetry circuit achieves 7.2 pArms noise in an 11.5-kHz bandwidth and only consumes 21-μ W power and 0.06 mm2 area per readout channel. Cyclic voltammetry experiments in a potassium ferricyanide solution and patch-clamp whole-cell experiments were performed to validate the circuit's feasibility for electrochemical biosensor applications.

A 0.23- $\mu \text{g}$ Bias Instability and 1- $\mu \text{g}/\surd $ Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout circuit architecture. A phase lock loop (PLL) with a hybrid and antinoise folding PFD is employed to sustain the oscillation of the MEMS oscillator, and the oscillation amplitude is set by an external reference. In addition, a sigma-delta frequency-to-digital converter is combined with the PLL to digitize the accelerometer’s frequency output for low power consumption. The MEMS transducer and the readout circuit are fabricated in an 80- $\mu \text{m}$ SOI and standard 0.35- $\mu \text{m}$ CMOS process, respectively. The SOA achieves 0.23- $\mu \text{g}$ bias instability and 1- $\mu \text{g}$ /Hz $^{1/2}$ acceleration noise density with a ±30 g full-scale, which are equivalent to 4-ppb relative instability and 17-ppb/Hz $^{1/2}$ relative acceleration noise density. It only consumes 2.7 mW under a 1.5 V supply.

Integrated chip of capacitive three‐axis accelerometer and sensing circuit

A CMOS-microelectromechanical system 0.18 µm process of the Taiwan Semiconductor Manufacturing Company is used to design an integrated chip of a capacitive three-axis accelerometer and a sensing circuit. The sensing architecture uses capacitive sensing principles, and the three axes are integrated on the same structure and share the same mass. The three-axis design method can not only reduce the chip area but also has good sensing ability. The readout circuit architecture combines two capacitor voltage converters and a subtraction amplifier, which can change the sensing signal into voltage amplitude values. As a result, the total chip area is 1.6 × 2.0 mm2, and the sensing range is from 1 to 4 G. The simulated sensitivities of X, Y, and Z are 34.8, 20.0, and 13.7 mV/G, respectively.

38.1: A Low‐Power Fast Readout Circuit using a Dual‐Mode Sensing Algorithm for Medium‐Size Capacitive Touch Screen Panels

AbstractA new readout circuit architecture for capacitive touch screen panels (TSPs) is introduced to enhance the reporting rate and to improve the signal to noise ratio (SNR) with low power consumption. The proposed Dual‐Mode Sensing (DMS) method finds the actual touch spots without feedback from the TSP to the MCU. In addition, the effect of noise coupled to the touch signal is reduced owing to the averaging effect of the proposed continuous‐time integration (CTI) technique. The circuit was designed for a 0.35 μm CMOS technology. The proposed sensing scheme shows a 257 Hz reporting rate under a simultaneous 10 touch condition on a 10.1 inch TSP, providing a 33 dB SNR with power consumption of 679 μW from a 3.3V supply.

Readout circuit with dual switching mode design for infrared focal plane arrays

The paper proposes a readout circuit architecture with adjustable integration time for dual-band infrared detectors. The readout circuit uses direct injection to be combined with a capacitive trans-impedance amplifier. The amplifier is sharing between two pixels to reduce the complexity of the readout circuit. The proposed device reduces power consumption and area overhead compared to traditional structures. An experimental chip was fabricated using the TSMC 0.35μm 2P4M 5V process. The resulting unit pixel layout area is 40μm×40μm with input photocurrent ranging from 0.11pA to 50nA. CTIA mode is applicable from 0.11pA to 10nA, while DI mode is applicable from 3.3pA to 50nA. The maximum operating frequency of the chip are 4MHz. The CTIA output swing is 1.2V, the DI output swing is 2V. The signal to noise ratio of the readout circuit is 65dB and power consumption is less than 9.6mW.

LWIR 256 × 256 HgCdTe focal plane array operating at 88 K

A 256 × 256 IRCMOS array with a 35 μm pitch operating at 88 K and above 10 μm has been developed at LETI/LIR. High performance has been obtained using, on the one hand, a reduced dark current detector technology and, on the other, a new readout circuit architecture which maximises both charge handling capacity and responsivity. We have measured a NEDT of 13 mK at 88 K for a cutoff wavelength of 10.1 μm. A description of the array is given and the main electro-optical characteristics of the component are presented.