Readout Channels Research Articles

A microwave SQUID multiplexer optimized for bolometric applications

A microwave superconducting quantum interference device multiplexer has been optimized for reading out large arrays of superconducting transition-edge sensor (TES) bolometers. We present the scalable cryogenic multiplexer chip design that may be used to construct an 1820-channel multiplexer for the 4–8 GHz rf band. The key metrics of yield, sensitivity, and crosstalk are determined through measurements of 455 readout channels, which span 4–5 GHz. The median white-noise level is 45 pA/Hz, evaluated at 2 Hz, with a 1/f knee ≤ 20 mHz after common-mode subtraction. The white-noise level decreases the sensitivity of a TES bolometer optimized for detection of the cosmic microwave background at 150 GHz by only 3%. The measured crosstalk between any channel pair is ≤ 0.3%.

Analog CMOS Readout Channel for Time and Amplitude Measurements With Radiation Sensitivity Analysis for Gain-Boosting Amplifiers

The front-end readout channel consists of a charge sensitive amplifier (CSA) and two different unipolar-shaping circuits to generate pulses suitable for time and energy measurement. The signal processing chain of the single channel is built of two different parallel processing paths: a fast path with a peaking time of 30 ns to obtain the time of arrival for each particle impinging the detector; and a slow path with a peaking time of 400 ns dedicated for low noise amplitude measurements, which is formed by a pole-zero cancellation circuit and a 4th order complex shaper based on a bridged-T architecture. The tunability of the system is accomplished by the discharge time constant of the CSA in order to accommodate various event rates. The readout system has been implemented in a 180 nm CMOS technology with the size of 525 μm x 290 μm. The building blocks use compact gain-boosting techniques based on quasi-floating gate (QFG) transistors achieving accurate energy measurement with good resolution. The high impedance nodes of QFG transistors require a detailed study of sensitivity to single-effect transients (SET). After carrying out this study, this paper proposes a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation. The nonlinearity of the CSA-slow-shaper has been found to be less than 1% over a 10-70 fC input charge. The power dissipation of the readout channel is 4.1 mW with a supply voltage of 1.8 V.

Research on the readout noise suppression method for digital correlated double sampling

As the areas of CCD detectors and CCD mosaics have become larger and larger, the number of readout channels in astronomical cameras has increased accordingly to keep the image readout time within an acceptable range. For the large area cameras or the mosaic cameras, the analog Correlated Double Sampling (aCDS) circuit used in traditional astronomical cameras for suppressing readout noise is difficult to integrate into the camera controllers within the constraints of the space and energy consumption. Recently, digital CDS (dCDS) technology has been developed to solve this problem, which also offers novel analysis and noise suppression methods. In this study, a mathematical model is presented to conveniently analyze the frequency characteristic of a dCDS circuit, which is then simulated by a numerical method for investigating the noise suppression capability with different sampling weights. Importantly, using this model, the extreme point with lowest readout noise can be predicted for a certain dCDS model; and for a specific CCD readout frequency, readout noise can be suppressed by selecting the proper dCDS model. A testing system is then constructed for validating the efficiency of the proposed method.

Quality assurance test of silicon photomultipliers and electronic boards for STAR event plane detector

The event plane detector (EPD), installed in the Solenoid Tracker at the Relativistic Heavy-Ion Collider located at the Brookhaven National Laboratory, is a plastic scintillator-based device that measures the reaction centrality and event plane in the forward region of the relativistic heavy-ion collisions. We used silicon photomultiplier (SiPM) arrays to detect the photons produced in the scintillator via the fiber connection. Signals from the SiPM arrays were amplified by the front-end electronic (FEE) board and sent to the analog-to-digital converter (ADC) boards for further processing via the receiver (RX) board. The full EPD system consisted of 24 super-sectors (SSs); each SS was equipped with two SiPM boards, two FEE boards and two RX boards, and they corresponded to 744 readout channels. All these boards were mass produced at the University of Science and Technology of China, with dedicated quality assurance (QA) procedures applied to identify any problems before deployment. This article describes the details of the QA method and the related test system. The QA test results are presented along with the discussions.

Development of Detector Control System (DCS) for forward hadron calorimeters in the BM@N and the MPD experiments

The BM@N and the MPD experiments at NICA facility (Dubna, Russia) will use the forward hadron calorimeters (FHCal) for centrality and reaction plane determination in the heavy ion collisions. The FHCal is a modular lead/scintillator sampling calorimeter with longitudinal segmentation. The light from each longitudinal section in module is detected with one silicon photomultiplier (MPPC) with sensitive area of 3x3mm2. In total, the FHCal at the BM@N experiment has 438 readout channels, while two MPD calorimeter arms have 616 readout channels. This article shows the DCS design with hardware and software development for these calorimeters. The DCS will be used to control and correct the bias voltages with temperatures of MPPCs. An integration into the main DCS systems for both experiments are discussed.

Read-out analog channel with interpolator for signal peak finding

A prototype of an analog channel with a digital processing system for reading signals from GEM detectors is presented. Each channel consists of a charge-sensitive amplifier, a shaper, a switch, an amplifier and a 10-bits ADC. The data from the ADC is processed by the digital system based on an interpolator to find signal peaks. The interpolator uses a 6th order Lagrange polynomial. It maintains peak detection accuracy within 1.1 LSB at 25 MHz ADC sampling rate and 270 ns shaper peaking time.

Multiple time-over-threshold readout electronics for fast timing and energy resolving in a SiPM-based positron annihilation lifetime spectrometer

Fast timing and energy resolving capabilities are crucial for a silicon-photomultiplier-based positron annihilation lifetime (SiPM-PAL) spectrometer. Time-over-threshold (ToT) offers an attractive method for combining timing and energy encoding with the advantage of simplicity in electronics implementation and SiPM readout. However, single ToT is not appropriate for a SiPM-PAL spectrometer because of its poor energy linearity and limited energy range. In this work, a multi-ToT readout circuit for a SiPM-PAL spectrometer is developed. Each readout channel uses only a pre-amplifier and a comparator for timing, three comparators for energy resolving, resistors, and capacitors. A simple pulse area estimation method using multi-ToT pulse widths and fixed threshold voltages for energy resolving is presented and evaluated. The energy performance and pulse area integral nonlinearity (INL) are investigated using 22Na, 60Co, and 137Cs γ sources with a SiPM-based scintillation detector. For pulse area spectra using the proposed method, multi-ToT (triple and dual threshold cases) resolves γ energies much better than does single ToT. Using triple-ToT, the pulse area linearity in INL in the energy range of 511–1333 keV is superior than 4.21%, which is at least 25% better than that with dual-ToT. Excellent coincidence resolving times of 161.5 ± 1.4 ps and 162.7 ± 1.3 ps in full width at half maximum are achieved using triple-ToT and dual-ToT, respectively, for 3 mm\\;×\\;3 mm\\;×\\;5 mm lutetium-fine-silicate scintillators. The quantitative energy and timing results show that the multi-ToT circuit is suitable for the readout electronics of a SiPM-PAL spectrometer.

The development of the Front-End Boards for the small-strip Thin Gap Chambers detector system of the ATLAS Muon New Small Wheel upgrade

The ATLAS experiment at CERN is scheduled to replace the innermost station of its Muon Spectrometer in the forward region during its Phase-I upgrade in order to enhance the capabilities on triggering and tracking of high transverse momentum muons towards high luminosity LHC runs. The New Small Wheel (NSW), a completely new detector system to be built, is composed of two novel gaseous detectors: Micro-mesh Gaseous Structure (Micromegas) and the small-strip Thin Gap Chamber (sTGC). The sTGC sub-system is the primary trigger detector. It will be equipped with radiation-tolerant, low-latency electronics for reading out over 400,000 channels to identify the bunch crossing time of proton-proton collisions spaced by 25 ns, as well as to collect fine strip charge information for the charged track reconstruction. In this paper, we present the design and development of a set of Front-End Boards (FEBs) for the sTGC detector system. The major challenges in the design will be discussed. These include the accommodation of a few hundred readout channels per single board in a very constrained space, a tight requirement for the Electrostatic Discharge (ESD) protection of 130 nm ASICs, and customized analog input circuits to handle the high rate and high charge signals from the sTGC detectors. Moreover, the FEBs have to incorporate a few hundred parallel inter-chip links at 320 Mbps and several low-latency serial links operating at 4.8 Gbps for the Level-1 and trigger data readout. The characterization of the FEBs performance, both off-detector and on-detector, will be shown.

Design and first performance results of waveform sampling readout electronics for Large Area Picosecond Photodetector

Large Area Picosecond Photodetectors (LAPPD) are a new generation of microchannel plate photomultipliers being manufactured by Incom. These devices feature large sensitive area of 350 cm2, high quantum efficiency (∼ 20%), and tens of picosecond single photon timing resolution. LAPPDs use an anode structure with 28 striplines, allowing for spatial resolution of 1 ÷ 3 mm while minimizing the number of readout channels. In this report, we present our design of integrated readout electronics for the LAPPD . These electronics read out all 2×28 channels of a stripline-anode LAPPD . Waveform sampling at up to 5GSPS is performed by 8 DRS4 switched-capacitor array ASICs. All DRS4 channels are digitized in parallel with two 32-channel ADCs. An on-board FPGA coordinates digitization and readout of waveforms, and could further be expanded to include some waveform processing. Data packages built in the FPGA are sent to a data acquisition system (DAQ) via optical fiber, with a baseline Gigabit Ethernet interface implemented entirely on the FPGA . The electronics is designed to accommodate different triggering options: self-triggering using DRS4 transparent mode and external triggering, making event control very flexible. Further flexibility is enhanced with embedded software for an on-FPGA soft-core processor, as well as DAQ readout and control software. The device is plug and play with any existing IP network. An open-source ecosystem is being developed to provide full control of the device operation and an easy way to integrate it to any environment. In the report we describe the status of the electronics development, its firmware and readout software. Also the results of the first tests of the electronics with the LAPPD devices will be presented.

The FAIR Phase 0 program of the CBM TOF

In order to provide particle identification (PID) of charged hadrons at the future high-rate Compressed Baryonic Matter (CBM) experiment, the TOF group has developed a large-area Time-of-Flight (ToF) wall equipped with Multi-gap Resistive Plate Chambers (MRPC) capable to operate at incident particle fluxes of up to 30 kHz/cm2. Prior to its destined operation at the Facility for Antiproton and Ion Research (FAIR)—starting in 2025—this high-rate timing MRPC technology will be used for physics research at two scientific pillars of the FAIR Phase-0 program: the end-cap TOF upgrade of the STAR experiment at RHIC and the mini-TOF (mTOF) wall of the mini-CBM (mCBM) experiment at Schwerionensynchrotron18 (SIS18). At STAR, the fixed-target program of the Beam Energy Scan II (BES-II) will rely on 108 CBM MRPC detectors for forward PID at trigger rates of up to 2 kHz. At mCBM, high-performance benchmark runs of Lambda-baryon production at top SIS18 energies and CBM design interaction rates of 10 MHz will become feasible with a PID backbone consisting of 25 CBM MRPC detectors. Apart from the physics perspective, these pre-FAIR involvements will help gathering experience in operating the final CBM TOF wall comprising about 1500 MRPC detectors and 110,000 readout channels. The status of the FAIR phase 0 program will be discussed.

LTARS: analog readout front-end ASIC for versatile TPC-applications

We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion μ-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the Silterra 180 nm CMOS technology and has 16 readout channels. We carried out the performance test at room temperature and the results showed an equivalent noise charge of 2695±71 e− (rms) with a detector capacitance of 300 pF. The dynamic range was measured to be 20–100 fC in the low-gain mode and 200–1600 fC in the high-gain mode within 10% integral nonlinearity at room temperature. We also tested the performance at the liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time. Based on these results, we also discuss a unique simulation methodology for future cold-electronics development. This method can be applicable to design the electronics used at low temperature.

A possible LHCb Luminosity Monitor based on the Muon System

The Muon System of the LHCb experiment, after the ongoing upgrade, will be composed of 4 stations which comprise 1104 multi-wire-proportional-chambers (MWPC) with order of {105} readout channels. We are investigating the possibility of using the rates recorded on the Muon chambers to measure the luminosity. A first study in this direction was performed analyzing the rates measured during special runs taken in 2012 at instantaneous luminosities up to {1033 cm−2s−1} and correlating them to the calorimeter-based measurements. After the correction for the dead time of the electronics the results were very promising allowing to estimate the correct values of luminosity with a precision better than 1%. The same method was also applied to a new set of runs taken in 2018 with a different LHC filling scheme necessary to achieve even higher values of instantaneous luminosity. Both the analyses will be presented to explore the possibility of using the Muon system to monitor LHCb luminosity in future runs without the support of the calorimeter.

Development of a low-noise front-end ASIC for CdTe detectors

We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 μm CMOS technology (X-Fab XH035), consists of 64 readout channels and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9e−± 11.3e− (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons within the energy from 6.4 keV to 122.1 keV are detected. Based on the experimental results, we propose a new low-noise readout architecture making use of a slew-rate limited mode at the shaper followed by a peak detector circuit.

Wearable Multiple Modality Bio-Signal Recording and Processing on Chip: A Review

Remote home monitoring via wearables is rapidly gaining popularity, thanks to ever more complex vital signs recording and data analytics that are embedded into single devices. True system-on-chips (SoCs) push the envelope of power and form factor, while wearables are becoming more common-place, novel health sensing paradigms appear. Non-contact sensing technologies enable vital signs sensing without requiring any physical contact with the human body. This article reviews existing multiple-modality bio-signal recording and processing SoCs, circuit techniques for individual bio-signal readout channels including electrocardiography (ECG), Electroencephalography (EEG), Bio-impedance (BioZ), photoplethysmography (PPG), and non-contact sensing with high user comfort. The state-of-the-art wearable sensor interfaces and systems together with future development trends are provided.

Design of prototype Front-End Electronics for the Gamma-Gamma collider

The Gamma-Gamma collider is a scientific facility proposed in China to observe two unique interactions at the center-of-mass energy of 1–2 MeV, namely γγ scattering and electron-positron pairs. In the experiment, two γ beams generated by the Compton back-scattering of high-energy electron beams (∼200 MeV) and high-intensity laser beams will collide at the interaction point, and the products will be collected by CsI(Na) crystals and plastic scintillators, and then converted into electric signals by silicon photomultiplier (SiPM) detectors. In this paper, a prototype Front-End Electronics (FEE) is implemented to verify the design requirements concerning the noise level (no more than 3 mV), high sampling rate (1 GS/s) and low power consumption. The prototype FEE comprised 8 differential drivers, 2 low-power switch capacitor array (SCA) DRS4 chips, and an 8-channel Analog-to-Digital Converter (ADC). The input signals were first stored in DRS4 chips for time stretching, then digitized by the ADC, and finally sent to back-end electronics via an optical link. The noise (RMS) of each readout channel on the prototype FEE was less than 3 mV after offset correction, and the ENOB of the channels was better than 6.7 bit when the frequency of input sine waves was less than 70 MHz and the sampling rate of the DRS4 was 1 GS/s. Therefore, the performance of the prototype FEE meets the requirements of the Gamma-Gamma collider.

New 3D fine-grained scintillation detector for the T2K experiment

The main goal of the T2K long-baseline neutrino experiment is the precise measurement of the parameters of neutrino oscillation and the search for CP-violation in the lepton sector. In 2017, the T2K collaboration launched the Near Detector Upgrade project. This upgrade aims to reduce the systematic errors of the oscillation parameters from 6–7% to 3–4%. In order to accomplish such goal, ND280 Upgrade proposes to implement new upstream trackers to improve the wide angle acceptance and low momentum threshold. One of the novel technologies introduced in ND280 Upgrade is super fine-grained (SuperFGD) scintillator target with 3D WLS fiber readout. The detector will consist of about 2 million (192× 184× 56) scintillation cubes of 1-cm size. Each cube has three orthogonal holes for WLS fibers to provide 3D optical readout. The total mass of the detector is about 2 tons and the number of the readout channels is about 60,000. This paper presents the current status of the development of this detector.

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section.

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC is presented for the application of local activation imaging in nerve section. It is increasingly known that the monitoring and control of nerve signals can improve physical and mental health. Major nerves, such as the vagus nerve and the sciatic nerve, consist of a bundle of fascicles. Therefore, to accurately control a particular application without any side effects, we need to know exactly which fascicle was activated. The only way to find locally activated fascicle is to use electrical impedance tomography (EIT). The ASIC to be introduced is designed for neural EIT applications. A neural impedance sensing ASIC was implemented using CMOS 180-nm process technology. The integrated input referred noise was calculated to be 0.46 μVrms (noise floor 10.3 nVrms/rt Hz) in the measured noise spectrum. At an input of 80 mV, the squared correlation coefficient for linear regression was 0.99998. The amplification gain uniformity of 32 channels was in the range of + 0.23% and - 0.29%. Using the resistor phantom, the simplest model of nerve, it was verified that a single readout channel could detect a signal-to- noise ratio of 75.6 dB or more. Through the reservoir phantom, real-time EIT images were reconstructed at a rate of 8.3 frames per second. The developed ASIC has been applied to in vivo experiments with rat sciatic nerves, and signal processing is currently underway to obtain activated nerve cross-sectional images. The developed ASIC was also applied to in-vivo experiments with rat sciatic nerves, and signal processing is currently underway to obtain locally activated nerve cross-sectional images.

In-depth evaluation of TOF-PET detectors based on crystal arrays and the TOFPET2 ASIC

In recent years high efforts have been devoted to enhance spatial and temporal resolutions of PET detectors. However, accurately combining these two main features is, in most of the cases, challenging. Typically, a compromise has to be made between the number of readout channels, scintillator type and size, and photosensors arrangement if aiming for a good system performance, while keeping a moderate cost. In this work, we have studied several detector configurations for PET based on a set of 8×8 Silicon Photomultiplier (SiPMs) of 3×3 mm2 active area, and LYSO crystal arrays with different pixel sizes. An exhaustive evaluation in terms of spatial, energy and timing resolution was made for all detector configurations. In some cases, when using pixel sizes different than SiPM active area, a significant amount of scintillation light may spread among several SiPMs. Therefore, we made use of a calibration method considering the different SiPM timing contributions. Best Detector Time Resolution (DTR) of 156 ps FWHM was measured when using 3×3 mm2 crystal pixels directly coupled to the 3×3 mm2 SiPMs. However, when using 1.5 mm crystal pixels with the same photosensor array, although we could clearly resolve all crystal pixels, an average DTR of 250 ps FWHM was achieved. We also shed light in this work on the timing dependency of the crystal pixel and photosensor alignment.

Characterization of four readout circuits for an MR compatible, preclinical PET detector

We are building a high sensitivity preclinical PET/MRI insert using a highly multiplexed light sharing PET module. Each module incorporates four 19 × 19 arrays of 1 × 1 × 20 mm3 LYSO crystals with dual-ended DOI encoding readout, requiring 32 readout channels for positioning and eight channels for timing. These constraints necessitate compact, robust electronics for digitization. We have characterized four linearized time-over-threshold circuits based on these detector requirements. The four circuits allow for high channel density and can digitize signals from highly multiplexed light sharing detectors. Each circuit digitizes one channel of a multiplexed SiPM array, yielding a binary output that interfaces directly with an FPGA. Using the optimal circuit, we have characterized the performance of a pair of PET modules. The four circuits were characterized based on linearity of the 22Na photopeak positions and energy resolution at 511 keV, as well as separation of elements in a 10 × 10 array of 1.2 mm LYSO crystals coupled with a specular reflector. Practical measures of performance were comparable to those obtained with a DRS evaluation board, which served as a reference acquisition system. The ratio of the 22Na photopeak positions was 2.0 for each circuit and the reference system, implying 20% saturation due to the SiPM. PET energy resolution of the optimal circuit was 11.8% FWHM for a single crystal versus 12.6% for the reference system, and crystals were equally well separated in all cases. PCBs implementing the optimal readout circuit were fabricated and used to construct two complete detector modules. Crystals in each of the four blocks in the module were well resolved, with a mean energy resolution of 24.4 ± 4.7%. Two modules operating in coincidence showed a single detector timing resolution of 3.0 ns, which is appropriate for preclinical applications.

TERA: Throughput-Enhanced Readout ASIC for High-Rate Energy-Dispersive X-Ray Detection

This work presents throughput-enhanced readout ASIC (TERA), an integrated multichannel analog pulse processor (APP), suitable for processing signals generated from solid-state detectors, such as silicon drift detectors (SDDs) coupled to pulsed reset-type charge-sensitive amplifiers (CSAs). In particular, this development targets applications at high count rates (≈Mcps) in energy-dispersive X-ray spectroscopy. The demonstrator chip is composed of four parallel readout channels. Each channel includes a seventh-order semi-Gaussian shaping amplifier with controllable shaping times and full-scale ranges, followed by a peak stretcher and switched-capacitor analog memory. Each channel is also equipped with a dedicated peak detector and a novel pile-up rejection (PUR) logic. Each pair of channels can be optionally digitized by a 12-bit on-chip successive-approximation-register (SAR) analog-to-digital converter (ADC), providing a digital output at a maximum sampling rate of 2.5 Msps. The architecture achieves high throughput and satisfactory energy resolution. In fact, in 55Fe spectroscopy measurements, when using the shortest shaping pulsewidth of 200 ns, a full-width at half-maximum (FWHM) Mn $\text{K}\alpha $ line of 159.4 eV (12.5 $\text{e}^{-}_{\text {rms}}$ ) was obtained at low rates (10 kcps). This energy resolution can be achieved, thanks to the minimization of the effect of the ballistic deficit, achieved by optimizing the SDD detector in terms of optimum biasing, low operating temperature (−37 °C), and small size (1-mm diameter). At 1.61 Mcps/channel input rate, an output count rate of 1.09 Mcps/channel and a resolution of 205.1 eV (19.7 $\text{e}^{-}_{\text {rms}}$ ) were achieved with a 4-mm-diameter SDD and optimum PUR settings. Simultaneous multichannel acquisition has been successfully performed. Such high-rate performances are, to our knowledge, the best ones reported so far for an APP, based on a spectroscopy-grade application-specific integrated circuit (ASIC), and very close to those achievable by a standard digital pulse processor (DPP). Therefore, TERA can represent an attractive, compact, and scalable pulse processing solution for high-rate multichannel energy-dispersive X-ray detection systems.