Readout Integrated Circuit Research Articles

TexSe1-x Shortwave Infrared Photodiode Arrays with Monolithic Integration.

TexSe1-x shortwave infrared (SWIR) photodetectors show promise for monolithic integration with readout integrated circuits (ROIC), making it a potential alternative to conventional expensive SWIR photodetectors. However, challenges such as a high dark current density and insufficient detection performance hinder their application in large-scale monolithic integration. Herein, we develop a ZnO/TexSe1-x heterojunction photodiode and synergistically address the interfacial elemental diffusion and dangling bonds via inserting a well-selected 0.3 nm amorphous TeO2 interfacial layer. The optimized device achieves a reduced dark current density of -3.5 × 10-5 A cm-2 at -10 mV, a broad response from 300 to 1700 nm, a room-temperature detectivity exceeding 2.03 × 1011 Jones, and a 3 dB bandwidth of 173 kHz. Furthermore, for the first time, we monolithically integrate the TexSe1-x photodiodes on ROIC (64 × 64 pixels) with the largest-scale array among all TexSe1-x-based detectors. Finally, we demonstrate its applications in transmission imaging and substance identification.

Enhancing Performance in Top‐Illuminated Shortwave Infrared Organic Photodetectors via Microcavity Resonance

AbstractShortwave infrared (SWIR) image sensors have unique functions in many optical applications, leading to widespread attention in developing next‐generation materials and photodetector technologies. Organic photodetectors (OPDs) are highly promising due to their flexibility in molecular design and processability. However, integrating OPDs with silicon readout integrated circuits (ROICs) poses numerous challenges, often resulting in underestimated device performance and limiting technological progress. To address the requirements of integrating top‐illuminated OPD with ROICs and to enhance the external quantum efficiency (EQE), optical microcavities are introduced into the OPDs. The EQE in the SWIR region can be effectively enhanced by properly adjusting the thicknesses of the photoactive layer (PAL) and interlayers. Simulations of the optical field distribution further support the active functions of the microcavity structure. The spatial variation of the microcavities allows the spectral response to shift from 1000 to 1400 nm, and the optimized device achieves an EQE of 25.8% at 1260 nm. Finally, the OPDs are integrated with a silicon‐based test kit, and the results reveal comparable sensing performance, demonstrating the high potential of microcavity resonance for device integration. This design effectively improves the integration of OPDs with traditional ROICs and advances SWIR‐based organic image sensor technology further toward commercialization.

An Ultrasensitive Molecularly Imprinted Point-Of-Care Electrochemical Sensor for Detection of Glial Fibrillary Acidic Protein.

Accurate assessment of neurological disease through monitoring of biomarkers has been made possible using the antibody-based assays. But these assays suffer from expensive development of antibody probes, reliance on complicated equipments, and high maintenance costs. Here, using the novel reduced graphene oxide/polydopamine-molecularly imprinted polymer (rGO/PDA-MIP) as the probe layer, a robust electrochemical sensing platform is demonstrated for the ultrasensitive detection of glial fibrillary acidic protein (GFAP), a biomarker for a range of neurological diseases. A miniaturized integrated circuit readout system is developed to interface with the electrochemical sensor, which empowers it with the potential to be used as a point-of-care (POC) diagnostic tool in primary clinical settings. This innovative platform demonstrated good sensitivity, selectivity, and stability, with imprinting factor evaluated as 2.8. A record low limit-of-detection (LoD) is down to 754.5 agmL-1, with a wide dynamic range from 1 to 106 fgmL-1. The sensing platform is validated through the analysis of GFAP in clinical plasma samples, yielding a recovery rate range of 81.6-108.8% compared to Single Molecule Array (Simoa). This cost-effective and user-friendly sensing platform holds the potential to be deployed in primary and resource-limited clinical settings for the assessment of neurological diseases.

A universal optoelectronic imaging platform with wafer-scale integration of two-dimensional semiconductors

Photodetectors (PDs) are crucial in modern society, as they enable the detection of a diverse range of light-based signals. With the exponential increase in their development, materials are being used to create a wide range of PDs that play critical roles in enabling various applications and technologies. Image sensor technology has been hindered due to the lack of a universal system that can integrate all types of PDs with silicon-based readout integrated circuits (ROICs). To address this issue, we conducted experiments using two-dimensional materials as an example. We fabricated high-performance MoS2/MoTe2-based photodetectors and identified the most suitable ROICs to pair with them. This established a solid foundation for further research in the field of image sensors. We developed and implemented a versatile testing system that uses a printed circuit board to connect the PD and ROIC. After the ROIC generates the sampled signal, it is collected and processed by algorithms, which overcome device uniformity limitations and produce a high-quality image that is visible to the naked eye. This universal system can be used with a wide range of PD and ROIC types made from different materials, making it highly convenient for diverse testing applications and the development of diverse image sensor types. This robust new platform is expected to spur further innovation and advancements in this rapidly developing field.

Microfluidic Lab-on-CMOS Packaging Using Wafer-Level Molding and 3D-Printed Interconnects.

Lab-on-a-chip (LoC) technologies continue to promise lower cost and more accessible platforms for performing biomedical testing in low-cost and disposable form factors. Lab-on-CMOS or lab-on-microchip methods extend this paradigm by merging passive LoC systems with active complementary metal-oxide semiconductor (CMOS) integrated circuits (IC) to enable front-end signal conditioning and digitization immediately next to sensors in fluid channels. However, integrating ICs with microfluidics remains a challenge due to size mismatch and geometric constraints, such as non-planar wirebonds or flip-chip approaches in conflict with planar microfluidics. In this work, we present a hybrid packaging solution for IC-enabled microfluidic sensor systems. Our approach uses a combination of wafer-level molding and direct-write 3D printed interconnects, which are compatible with post-fabrication of planar dielectric and microfluidic layers. In addition, high-resolution direct-write printing can be used to rapidly fabricate electrical interconnects at a scale compatible with IC packaging without the need for fixed tooling. Two demonstration sensor-in-package systems with integrated microfluidics are shown, including measurement of electrical impedance and optical scattering to detect and size particles flowing through microfluidic channels over or adjacent to CMOS sensor and read-out ICs. The approach enables fabrication of impedance measurement electrodes less than 1 mm from the readout IC, directly on package surface. As shown, direct fluid contact with the IC surface is prevented by passivation, but long-term this approach can also enable fluid access to IC-integrated electrodes or other top-level IC features, making it broadly enabling for lab-on-CMOS applications.

Increasing the Position Resolution in Single Photon Counting Pixel Readout IC by Real-Time Interpixel Communications

Increasing the Position Resolution in Single Photon Counting Pixel Readout IC by Real-Time Interpixel Communications

Synergism in Binary Nanocrystals Enables Top-Illuminated HgTe Colloidal Quantum Dot Short-Wave Infrared Imager.

Thanks to their tunable infrared absorption, solution processability, and low fabrication costs, HgTe colloidal quantum dots (CQDs) are promising for optoelectronic devices. Despite advancements in device design, their potential for imaging applications remains underexplored. For integration with Si-based readout integrated circuits (ROICs), top illumination is necessary for simultaneous light absorption and signal acquisition. However, most high-performing traditional HgTe CQD photodiodes are p-on-n stack and bottom-illuminated. Herein, we report top-illuminated inverted n-on-p HgTe CQD photodiodes using a robust p-type CQD layer and a thermally evaporated Bi2S3 electron transport layer. The p-type CQD solid is achieved by exploring the synergism in binary HgTe and Ag2Te CQDs. These photodetectors show a room-temperature detectivity of 3.4 × 1011 jones and an EQE of ∼44% at ∼1.7 μm wavelength, comparable to the p-on-n HgTe CQD photodiodes. A top-illuminated HgTe CQD short-wave infrared imager (640 × 512 pixels) was fabricated, demonstrating successful infrared imaging.

An Experimental Investigation of Noise Sources’ Contribution in the Multi-Chip Module Open-Loop Comb-Drive Capacitive MEMS Accelerometer

The paper presents the noise analysis of a MEMS and ASIC readout integrated circuit (ROIC) constituting the accelerometer developed in the frame of the InnoReh project, aiming at the development of methods for monitoring patients with imbalance disorders. Several experiments were performed at different temperatures and in different configurations: ROIC alone, ROIC with emulated parasitic capacitances, MEMS and ROIC in separate packages, and MEMS and ROIC in a single package. Many noise/interference sources were considered. The results obtained experimentally were compared to the results of theoretical investigations and were within the same order of magnitude, although in practice, the observed noise was always greater than the theoretical estimation. The paper also includes an in-depth analysis to explain these differences. Moreover, it is argued that, in terms of noise, the MEMS sensing element, and not the ROIC, is the quality-limiting factor.

Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications

This paper presents the development and evaluation of a 128 × 128 Readout Integrated Circuit (ROIC) prototype, engineered for Short-Wave Infrared (SWIR) imaging at a specific target wavelength of 2.6 μm. Employing silicon-level verification, this work undertook an exhaustive analysis of the ROIC's performance, identifying key areas for enhancement to improve SWIR imaging systems. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) Focal Plane Arrays (FPAs), facilitating high-resolution imaging. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second. The fabricated chip show that the random noise level is 72.65 μVrms and Pixel-FPN is 21 LSBrms. This investigation lays a critical groundwork for future SWIR imaging advancements, providing valuable insights and methodologies to boost imaging performance in various applications.

Development and validation of a 64-channel ROIC prototype for SWIR line scan sensor applications

This paper introduces the development and validation of a 64-channel readout integrated circuit (ROIC) prototype, specifically engineered for short-wave infrared (SWIR) line scan sensors. The design of the prototype undergoes various evaluation through comprehensive silicon-level testing, ensuring its robust performance across a variety of operational modes. Key features such as capacitive transimpedance amplifier (CTIA) gain control and sensitivity control are examined, demonstrating the prototype's ability to handle different input currents and capacitance values with precision. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) pixels, facilitating high-resolution imaging. The prototype consumes 26.55 mW with A 3.3 V power supply. The fabricated chip show that the total random noise (RN) level is 128 μVrms and column fixed pattern noise (FPN) is 0.16 mVrms

A Dynamic Range Preservation Readout Integrated Circuit for Multi-Gas Sensor Array Applications

This study introduces a readout integrated circuit (ROIC) tailored for multi-gas sensor arrays featuring a proposed baseline calibration scheme aimed at mitigating the issue of sensor baseline variation. Unlike previous approaches, the proposed scheme stores each sensor’s baseline value and dynamically updates the signal extraction range accordingly during ROIC operation. This adjustment allows for the optimal use of the ROIC’s dynamic range, enhancing sensor uniformity and accuracy without the need for complex additional circuitry or advanced post-processing algorithms. We fabricated a prototype ROIC using a 180 nm CMOS process, achieving a low power consumption of 0.43 mW and a conversion rate of 50 kSPS. The prototype boasts an integrated noise level of 9.9 μVRMS across a frequency range of 0.1 Hz to 5 kHz and a dynamic range of 142.6 dB, coupled with superior linearity, indicated by a maximum integral non-linearity (INL) of −75.71 dB. This design significantly reduces sensor offset scattering to within 1 LSB of the A/D reference scale. In this study, the efficacy of the proposed scheme was validated using Figaro TGS-2600. The ROIC targets a sensitivity range from 0.54 to 0.23 for gas concentrations ranging from 5 ppm to 20 ppm and a resolution of 39 Ω for sensor resistance range from 10 kΩ to 90 kΩ. The enhancements in performance make the proposed ROIC a promising solution for precise gas concentration detection in sensor applications.

Mid-wavelength infrared focal plane array based on type II InAs/GaSb superlattices on InP substrate

We report the growth and characterization of band gap engineered mid-wavelength infrared photodiode, pBiBn, based on type-II InAs/GaSb superlattices on InP substrate. InP substrates are attractive material because they have high transmittance in the mid-wavelength infrared region and near thermal expansion coefficient to Si read-out IC (ROIC). Misfit dislocations due to lattice mismatch between GaSb and InP were successfully suppressed by thick GaSb buffer layer and two step growth of it. The photoluminescence (PL) spectrum from the absorption layers exhibits a peak wavelength of 5.01 μm at 77 K. The distinct PL peak was observed even at 120 K, indicating the excellent crystalline quality of T2SLs grown on an InP substrate. The dark current densities of 292 × 10−6 A/cm2 at 77 K and cut off wavelength of 5.15 μm at 80 K were measured, respectively. A clear image was obtained by fabricated focal plane array of 640 × 512 pixels with 15 μm pixel pitch, and NEDT and defective pixel rate was 50 mK and less than 1 % at 100 K, respectively.

Multiplexed Surface Electrode Arrays Based on Metal Oxide Thin-Film Electronics for High-Resolution Cortical Mapping.

Electrode grids are used in neuroscience research and clinical practice to record electrical activity from the surface of the brain. However, existing passive electrocorticography (ECoG) technologies are unable to offer both high spatial resolution and wide cortical coverage, while ensuring a compact acquisition system. The electrode count and density are restricted by the fact that each electrode must be individually wired. This work presents an active micro-electrocorticography (µECoG) implant that tackles this limitation by incorporating metal oxide thin-film transistors (TFTs) into a flexible electrode array, allowing to address multiple electrodes through a single shared readout line. By combining the array with an incremental-ΔΣ readout integrated circuit (ROIC), the system is capable of recording from up to 256 electrodes virtually simultaneously, thanks to the implemented 16:1 time-division multiplexing scheme, offering lower noise levels than existing active µECoG arrays. Invivo validation is demonstrated acutely in mice by recording spontaneous activity and somatosensory evoked potentials over a cortical surface of ≈8×8mm2 . The proposed neural interface overcomes the wiring bottleneck limiting ECoG arrays, holding promise as a powerful tool for improved mapping of the cerebral cortex and as an enabling technology for future brain-machine interfaces.

Double‐ended passivator enables dark‐current‐suppressed colloidal quantum dot photodiodes for CMOS‐integrated infrared imagers

AbstractLead sulfide (PbS) colloidal quantum dot (CQD) photodiodes integrated with silicon‐based readout integrated circuits (ROICs) offer a promising solution for the next‐generation short‐wave infrared (SWIR) imaging technology. Despite their potential, large‐size CQD photodiodes pose a challenge due to high dark currents resulting from surface states on non‐passivated (100) facets and trap states generated by CQD fusion. In this work, we present a novel approach to address this issue by introducing double‐ended ligands that supplementally passivate (100) facets of halide‐capped large‐size CQDs, leading to suppressed bandtail states and reduced defect concentration. Our results demonstrate that the dark current density is highly suppressed by about an order of magnitude to 9.6 nA cm−2 at −10 mV, which is among the lowest reported for PbS CQD photodiodes. Furthermore, the performance of the photodiodes is exemplary, yielding an external quantum efficiency of 50.8% (which corresponds to a responsivity of 0.532 A W−1) and a specific detectivity of 2.5 × 1012 Jones at 1300 nm. By integrating CQD photodiodes with CMOS ROICs, the CQD imager provides high‐resolution (640 × 512) SWIR imaging for infrared penetration and material discrimination.image

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs.

Environment-Adaptable Edge-Computing Gas-Sensor Device With Analog-Assisted Continual Learning Scheme

This paper presents a multi-gas sensor device whose structure is optimized for edge computing capability under internet of things (IoT) environments. Considering inherent sensor device characteristics susceptible to environmental factors like temperature and humidity, edge-computing capability for the on-site sensor calibration and pattern recognition (PR) is facilitated through a proposed analog-assisted continual learning scheme. An environment-adaptable continual learning (EACL) is proposed to combine multiple learning processes under different environments including chamber and on-site. Its computation burden is much relieved to be integrated into the edge device by adopting the analog-assisted structure, where a designed readout integrated circuit (ROIC) for automatic calibration normalizes gas-sensor data. For functional feasibility, an edge-computing IoT device prototype is manufactured with a fabricated ROIC and an in-house semiconductor-type sensor array, supporting wireless on-site monitoring platform interfaces. The environment-adaptable edge-computing capability is functionally verified through EACL-PR experiments on hazardous gases such as NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and CO under environmental factor variations. The average PR accuracy of 97% is achieved on several kinds of mixture gas patterns. The analog-assisted operation is verified to reduce the training cycles by 3 times while the EACL itself achieves 25% better efficiency.

AlGaN-Based Self-Powered Solar-Blind UV Focal Plane Array Imaging Photosensors: Material Growth, Device Preparation, and Functional Verification

This paper reports the development of hybrid AlGaN-based self-powered solar-blind ultraviolet (UV) focal plane array imaging photosensors from material growth and array preparation to functional verification. The detailed process starts with the epitaxial growth by metal-organic chemical vapor deposition (MOCVD). A high-quality AlN template is obtained on the 2-inch double-polished c-plane sapphire substrate by introducing a mesothermal AlN (MT-AlN) interlayer and adjusting the growth rate of the high-temperature AlN epilayer (HT-AlN). Then, a polarization-enhanced p-i-n structure photodetector material is grown on the AlN template. Subsequently, based on the p-i-n structural material, a 320×256 back-illuminated solar-blind photodiode array is fabricated and hybridized to a matching Si-based CMOS readout integrated circuit (ROIC) chip to form a focal plane detector. Solar-blind UV detection is observed throughout the array in the 262-281 nm spectral region with a peak external quantum efficiency (EQE) of 65.3% at zero-bias voltage (no antireflection coating) and a nanosecond transient response time at a reverse bias of 5 V. The visible response of the ROIC is eliminated by developing a masking technology that is opaque to visible light, which enables the focal plane detector to achieve a high UV/visible rejection ratio more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> .

In-pixel AI for lossy data compression at source for X-ray detectors

Integrating neural networks for data compression directly in the Read-Out Integrated Circuits (ROICs), i.e. the pixelated front-end, would result in a significant reduction in off-chip data transfer, overcoming the I/O bottleneck. Our ROIC test chip (AI-In-Pixel-65) is designed in a 65 nm Low Power CMOS process for the readout of pixelated X-ray detectors. Each pixel consists of an analog front-end for signal processing and a 10b analog-to-digital converter operating at 100KSPS. We compare two non-reconfigurable techniques, Principal Component Analysis (PCA) and an AutoEncoder (AE) as lossy data compression engines implemented within the pixelated area. The PCA algorithm achieves 50× compression, adds one clock cycle latency, and results in a 21% increase in the pixel area. The AE achieves 70× compression, adds 30 clock cycle latency, and results in a similar area increase.

A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes

This paper presents a multichannel readout integrated circuit (ROIC) with column-wise extended counting (EC) ADCs, which is targeted toward silicon diode uncooled infrared focal plane arrays (IRFPA). The column ADC features a direct connection with the detectors without extra pre-amplifiers. The ROIC incorporates 9-bit folding integration ADCs for coarse conversion and 5-bit single-slope ADCs for fine conversion. A pseudo-differential architecture combined with blind pixels is adopted to cancel even-order distortion. To improve linearity without increasing power consumption, a ping-pong integrator is adopted to reduce reset time by charging alternatively. A prototype consisting of 32 columns is fabricated in 180 nm 1P5M CMOS process for verification. The power consumption of one column is 50.5 μW. According to the measurement results, the input-referred noise is 1.21 LSB (2.36 μVrms), and the peak SNR is 82.5 dB. The INL and DNL are +2.43/-2.21 LSB and +0.33/-0.31 LSB, separately.

A CMOS Hall Sensors Array With Integrated Readout Circuit Resilient to Local Magnetic Interference From Current-Carrying Traces

This paper proposes a CMOS Hall sensors array with readout circuitry to counteract the magnetic interference from nearby conductors carrying high currents. The 3×3 Hall sensors array with current-spinning collects the spatial magnetic field information in a time-interleaved manner while the readout circuitry, formed by a capacitively-coupled instrumentation amplifier (CCIA) with T-capacitor feedback network, amplifies the transduced signals for subsequent processing. The calibration mechanism analyzes the magnetic field distribution on the array and separates the magnetic field component due to the environment and local perturbation from adjacent traces, enabling accurate detection of the environmental magnetic field. Prototyped in a 0.35-μm CMOS process, the Hall sensors array and readout circuit occupy an area of 2.2 × 2.2 mm2 and consume 3.5 mA of current under a 3.3-V supply. The hall sensors achieve an average sensitivity of 100 V/(A·T). The input-referred noise of the entire circuit is 0.128 μT/√Hz. With the interference cancellation scheme, the error in the magnetic field readings caused by a conductor 5 mm from the center of the chip carrying 3 A of current reduced from 120 to 5 μT, corresponding to a 24× improvement. Overall, the average error of the captured magnetic field after calibration reaches 0.9%.