Read-only Memory Research Articles

A Recursive Trigonometric Technique for Direct Digital Frequency Synthesizer Implementation

This paper presents a novel recursive trigonometry (RT) technique for direct digital frequency synthesizer (DDFS) implementations. Traditional DDFS systems on field programmable gate arrays (FPGAs) either require a substantial amount of read-only memory (ROM) space to store reference values or depend on intricate angle rotation functions to approximate trigonometric values. The proposed RT technique offers a DDFS architecture without using the lookup table (LUT) method, and it can enhance signal accuracy and minimize power consumption. The effectiveness of the proposed RT technique has been implemented in a 13.5 kHz 16-bit DDFS with a minimum of 18.91 mW and was tested on a Lattice FPGA. The effectiveness of the proposed RT technology is assessed by using different FPGA platforms in terms of accuracy, hardware resource efficiency, and power consumption, especially in generating cosine waveforms.

Design of Car Based on 5G Network Control

The role of smart cars is pivotal, and this project designs and implements a four-wheel vehicle control system leveraging 5G communication technology. The system aims to enhance the portability of smart cars, reduce their costs, enable remote control functionality, and improve mobility to meet the needs of modern Internet of Things (IoT) applications. The system integrates an ESP8266 Wi-Fi module with the Blinker IoT platform to enable remote, real-time control of car movement via a smartphone app. Using Access Point (AP) mode for fast network configuration, users can input Wi-Fi credentials and a Blinker key through a web interface for easy setup. Through the custom app interface, users can send commands to control the car’s forward, backward, turning, and stopping actions, as well as adjust speed and operation delay. Additionally, the system includes Electrically Erasable Programmable Read-Only Memory (EEPROM) data storage to ensure the persistent saving of configuration information, and it features a remote wireless camera for external monitoring of the car’s surroundings. The Android-based remote control design allows users to monitor and control the car’s movement anytime and anywhere. Experimental results show that the system is stable, provides smooth control, operates at low cost and low power consumption, and offers good portability. Therefore, this intelligent car control system offers valuable insights for smart car development and application. It can also be integrated with popular smart homes, IoT, and other emerging technologies, offering broad application potential and promising development prospects.

Constant-depth circuits for Boolean functions and quantum memory devices using multi-qubit gates

We explore the power of the unbounded Fan-Out gate and the Global Tunable gates generated by Ising-type Hamiltonians in constructing constant-depth quantum circuits, with particular attention to quantum memory devices. We propose two types of constant-depth constructions for implementing Uniformly Controlled Gates. These gates include the Fan-In gates defined by |x⟩|b⟩↦|x⟩|b⊕f(x)⟩ for x∈{0,1}n and b∈{0,1}, where f is a Boolean function. The first of our constructions is based on computing the one-hot encoding of the control register |x⟩, while the second is based on Boolean analysis and exploits different representations of f such as its Fourier expansion. Via these constructions, we obtain constant-depth circuits for the quantum counterparts of read-only and read-write memory devices – Quantum Random Access Memory (QRAM) and Quantum Random Access Gate (QRAG) – of memory size n. The implementation based on one-hot encoding requires either O(nlog(d)⁡nlog(d+1)⁡n) ancillae and O(nlog(d)⁡n) Fan-Out gates or O(nlog(d)⁡n) ancillae and 16d−10 Global Tunable gates, where d is any positive integer and log(d)⁡n=log⁡⋯log⁡n is the d-times iterated logarithm. On the other hand, the implementation based on Boolean analysis requires 8d−6 Global Tunable gates at the expense of O(n1/(1−2−d)) ancillae.

A Multi-Channel Urine Sensing Detection System Based on Creatinine, Uric Acid, and pH.

Urine analysis represents a crucial diagnostic technique employed in clinical laboratories. Creatinine and uric acid in urine are essential biomarkers in the human body and are widely utilized in clinical analysis. Research has demonstrated a correlation between the normal physiological concentrations of creatinine and uric acid in urine and an increased risk of hypertension, cardiovascular diseases, and kidney disease. Furthermore, the pH of urine indicates the body's metabolic processes and homeostatic balance. In this study, an integrated multi-channel electrochemical sensing system was developed, combining electrochemical analysis techniques, microelectronic design, and nanomaterials. The architecture of an intelligent medical detection system and the production of an interactive interface for smartphones were accomplished. Initially, multi-channel selective electrodes were designed for creatinine, uric acid, and pH detection. The detection range was 10 nM to 100 μM for creatinine, 100 μM to 500 μM for uric acid, and 4 to 9 for pH. Furthermore, interference experiments were also conducted to verify the specificity of the sensors. Subsequently, multi-channel double-sided sensing electrodes and function-integrated hardware were designed, with the standard equations of target analytes stored in the system's read-only memory. Moreover, a WeChat mini-program platform was developed for smartphone interaction, enabling off-body detection and real-time display of target analytes through smartphones. Finally, the aforementioned electrochemical detection electrodes were integrated with the smart sensing system and wirelessly interfaced with smartphones, allowing for intelligent real-time detection in primary healthcare and individual household settings.

Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation

To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of −88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems.

Field-programmable gate array implementation of efficient deep neural network architecture

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.

Increasing the period of active use of on-board electronic equipment of spacecraft

For electronic equipment of space systems, and primarily memory devices, the task of protection from the effects of ionizing cosmic radiation and other external factors that distort stored and processed information is relevant. This paper proposes a holographic coding method that allows you to restore information in the event of a large number of errors. The method is based on recording into memory, instead of the original digital hologram data, a virtual digital object corresponding to a data block. The divisibility property of a hologram is used, which makes it possible to reconstruct a recorded data block from its fragment. The achieved level of noise immunity is determined by the size of the hologram. For an 8-bit data block, recording a 256-bit hologram provides information recovery if 75 % of the recorded hologram is lost. The developed decoder corrects a package of dependent (grouping) errors that distort all bits of the hologram. The number of random independent errors that the decoder corrects can be up to 40 % of the recorded information. The information storage system, resistant to ionizing radiation, is a memory array of increased capacity, taking into account the selected redundancy factor, and a memory controller that performs holographic encoding when recording information and decoding with automatic error correction when reading information. The operating algorithm of the controller itself can be implemented in the form of a programmable logic integrated circuit, or stored in a read-only memory device that is not affected by ionizing radiation.

Optimizing Convolutional Neural Networks for Image Classification on Resource-Constrained Microcontroller Units

Running machine learning algorithms for image classification locally on small, cheap, and low-power microcontroller units (MCUs) has advantages in terms of bandwidth, inference time, energy, reliability, and privacy for different applications. Therefore, TinyML focuses on deploying neural networks on MCUs with random access memory sizes between 2 KB and 512 KB and read-only memory storage capacities between 32 KB and 2 MB. Models designed for high-end devices are usually ported to MCUs using model scaling factors provided by the model architecture’s designers. However, our analysis shows that this naive approach of substantially scaling down convolutional neural networks (CNNs) for image classification using such default scaling factors results in suboptimal performance. Consequently, in this paper we present a systematic strategy for efficiently scaling down CNN model architectures to run on MCUs. Moreover, we present our CNN Analyzer, a dashboard-based tool for determining optimal CNN model architecture scaling factors for the downscaling strategy by gaining layer-wise insights into the model architecture scaling factors that drive model size, peak memory, and inference time. Using our strategy, we were able to introduce additional new model architecture scaling factors for MobileNet v1, MobileNet v2, MobileNet v3, and ShuffleNet v2 and to optimize these model architectures. Our best model variation outperforms the MobileNet v1 version provided in the MLPerf Tiny Benchmark on the Visual Wake Words image classification task, reducing the model size by 20.5% while increasing the accuracy by 4.0%.

A novel one-time-programmable memory unit based on Schottky-type p-GaN diode

In this work, a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed. During the programming process, the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown, and the state is permanently preserved. The memory unit features a current ratio of more than 103, a read voltage window of 6 V, a programming time of less than 10−4 s, a stability of more than 108 read cycles, and a lifetime of far more than 10 years. Besides, the fabrication of the device is fully compatible with commercial Si-based GaN process platforms, which is of great significance for the realization of low-cost read-only memory in all-GaN integration.

Leveraging the page buffer data cache for enhanced programmability in NAND flash memories with on‐chip microcontrollers

AbstractThis paper proposes a simple yet effective scheme for NAND Flash memories that employ on‐chip microcontroller units (MCUs) to manage internal array operations. Through minimal hardware overhead, the proposed scheme enables—without mask revision— executing new or updated array operations by leveraging the page buffer data cache instead of the hard‐wired on‐chip read‐only memory (ROM) for MCU instruction memory. While not applicable to ordinary user operations, this approach presents significant advantages across various stages of NAND flash memory development and implementation.

An On-Board Executable Multi-Feature Transfer-Enhanced Fusion Model for Three-Lead EEG Sensor-Assisted Depression Diagnosis.

The development of affective computing and medical electronic technologies has led to the emergence of Artificial Intelligence (AI)-based methods for the early detection of depression. However, previous studies have often overlooked the necessity for the AI-assisted diagnosis system to be wearable and accessible in practical scenarios for depression recognition. In this work, we present an on-board executable multi-feature transfer-enhanced fusion model for our custom-designed wearable three-lead Electroencephalogram (EEG) sensor, based on EEG data collected from 73 depressed patients and 108 healthy controls. Experimental results show that the proposed model exhibits low-computational complexity (65.0K parameters), promising Floating-Point Operations(FLOPs) performance (26.6M), real-time processing (1.5s/execution), and low power consumption (320.8mW). Furthermore, it requires only 202.0MB of Random Access Memory(RAM) and 279.6KB of Read-Only Memory(ROM) when deployed on the EEG sensor. Despite its low computational and spatial complexity, the model achieves a notable classification accuracy of 95.2%, specificity of 96.9%, and sensitivity of 94.0% under independent test conditions. These results underscore the potential of deploying the model on the wearable three-lead EEG sensor for assisting in the diagnosis of depression.

OTK-based PUF CRP obfuscation for IoT device authentication

The use of a strong physical unclonable function (PUF) for device authentication in resource-limited settings is promising but susceptible to machine learning (ML) attacks. Several defenses have been suggested, but they often have drawbacks such as increased hardware requirements, compromised reliability, and limited effectiveness against sophisticated ML attacks. To overcome these challenges, a one-time key-based (OTK) obfuscation approach has been proposed aiming to bolster the security of robust PUFs when facing machine learning-based attacks. The main concept involves obtaining multiple stable responses from the PUF and selecting one as the initial key for challenge obfuscation. However, only the challenge input for the selected key is stored on the device side. The server stores all the stable challenge-response pairs and uses this selected key for the first authentication only. After every authentication, the input to the key is updated on both sides. For response obfuscation random number generated by the server is used. Our proposed method can effectively prevent ML attacks with minimal hardware requirements. Arbiter-PUF and Rely-PUF as case studies are analyzed. Experimental findings indicate that when applied to 64 × 64 Arbiter and Rely PUF, our method significantly reduces the effectiveness of various machine learning attacks, resulting in a prediction accuracy of approximately 50.6% and 50.96% respectively. This level of accuracy is comparable to random guessing. The 64-bit OTK-PUF boasts an impressively compact storage footprint, comprising merely 164 Look-Up Tables (LUTs), 276 flip-flops, and a 512-bit of read-only memory (ROM). The execution of the protocol on the Vitis platform takes a mere 0.02 s on the device side.

A Scalable Data Structure for Efficient Graph Analytics and In-Place Mutations

The graph model enables a broad range of analyses; thus, graph processing (GP) is an invaluable tool in data analytics. At the heart of every GP system lies a concurrent graph data structure that stores the graph. Such a data structure needs to be highly efficient for both graph algorithms and queries. Due to the continuous evolution, the sparsity, and the scale-free nature of real-world graphs, GP systems face the challenge of providing an appropriate graph data structure that enables both fast analytical workloads and fast, low-memory graph mutations. Existing graph structures offer a hard tradeoff among read-only performance, update friendliness, and memory consumption upon updates. In this paper, we introduce CSR++, a new graph data structure that removes these tradeoffs and enables both fast read-only analytics, and quick and memory-friendly mutations. CSR++ combines ideas from CSR, the fastest read-only data structure, and adjacency lists (ALs) to achieve the best of both worlds. We compare CSR++ to CSR, ALs from the Boost Graph Library (BGL), and the following state-of-the-art update-friendly graph structures: LLAMA, STINGER, GraphOne, and Teseo. In our evaluation, which is based on popular GP algorithms executed over real-world graphs, we show that CSR++ remains close to CSR in read-only concurrent performance (within 10% on average) while significantly outperforming CSR (by an order of magnitude) and LLAMA (by almost 2×) with frequent updates. We also show that both CSR++’s update throughput and analytics performance exceed those of several state-of-the-art graph structures while maintaining low memory consumption when the workload includes updates.

Characterization of Single Event Effect in a Radiation Hardened Programmable Read-Only Memory in a 130 nm Bulk CMOS Technology

The concept of memory that can only be read but cannot be changed seems strange at first. In reality, it is found that it has great application potential, such as the processor with a fixed purpose, the initial set value of the microprocessor BIOS, and these data are stored in Programmable Read-Only Memory (PROM) to quickly realize system functions. The PROM storage content is fixed, greatly simplifying his design. The radiation of space particles is the main factor causing the failure of the electronic system of spacecraft. The PROM storage array of the space electronic system is the most basic guarantee for the normal operation of the electronic system. The chip adopts domestic 130 nm standard technology of Complementary Metal Oxide Semiconductor (CMOS), Muller-C digital filter is used in the peripheral subsystem of PROM storage array, and the core cell uses Dual Interlocked Cell (DICE) and ring gate and other radiation hardening technologies to design a 32Kx8bit radiation resistant asynchronous programmable PROM. Pre-silicon of devices was verified by Technology Computer Aided Design (TCAD), and post silicon radiation verification was completed through radiation experiment. The post silicon radiation experiment showed that the total ionizing Dose (TID) capacity of the PROM chip was ≥100 Krad (Si), the critical value of single event upset (SEU) was ≥37.1 MeV·cm2/mg, the critical value of single event latch up was ≥98 MeV·cm2/mg, meeting the life requirements of the initial value storage of aerospace electronic systems. These performances ensure the reliable operation of the space electronic system after restart.

White Rabbit Expansion Board: Design, Architecture, and Signal Integrity Simulations

The White Rabbit protocol allows synchronization and communication via an optical link in an integrated, modular, and scalable manner. It provides a solution to those applications that have very demanding requirements in terms of synchronization. Field-programmable gate arrays are used to implement the protocol; additionally, special hardware is needed to provide the necessary clock signals used by the dual-mixer time difference for precise phase measurement. In the present work, an expansion board that allows for White Rabbit functionality is presented. The expansion board contains the oscillators required by the White Rabbit protocol, one running at 125 MHz and another at 124.922 MHZ. The architecture of this board includes two oscillator systems for tests and comparison. One is based on VCOs and another on crystal oscillators running at the desired frequencies. In addition, it incorporates a temperature sensor, from where the medium access control address is extracted, an electrically erasable programmable read-only memory, a pulse-per-second output, and a USB UART to access the White Rabbit IP core at the field-programmable gate array. Finally, to ensure the quality of the layout design and guarantee the level of synchronization desired, the results of the power and signal integrity simulations are also presented.

Quantum simulation of battery materials using ionic pseudopotentials

Ionic pseudopotentials are widely used in classical simulations of materials to model the effective potential due to the nucleus and the core electrons. Modeling fewer electrons explicitly results in a reduction in the number of plane waves needed to accurately represent the states of a system. In this work, we introduce a quantum algorithm that uses pseudopotentials to reduce the cost of simulating periodic materials on a quantum computer. We use a qubitization-based quantum phase estimation algorithm that employs a first-quantization representation of the Hamiltonian in a plane-wave basis. We address the challenge of incorporating the complexity of pseudopotentials into quantum simulations by developing highly-optimized compilation strategies for the qubitization of the Hamiltonian. This includes a linear combination of unitaries decomposition that leverages the form of separable pseudopotentials. Our strategies make use of quantum read-only memory subroutines as a more efficient alternative to quantum arithmetic. We estimate the computational cost of applying our algorithm to simulating lithium-excess cathode materials for batteries, where more accurate simulations are needed to inform strategies for gaining reversible access to the excess capacity they offer. We estimate the number of qubits and Toffoli gates required to perform sufficiently accurate simulations with our algorithm for three materials: lithium manganese oxide, lithium nickel-manganese oxide, and lithium manganese oxyfluoride. Our optimized compilation strategies result in a pseudopotential-based quantum algorithm with a total Toffoli cost four orders of magnitude lower than the previous state of the art for a fixed target accuracy.

Ukrainian National Encryption Standards for FPGA Based Embedded Systems

The paper presents the hardware implementation based on FPGA of the main cryptographic transformations of the symmetric transformation algorithm of DSTU 7624:2014 and the stream cipher of DSTU 8845:2019, which are the national encryption standards of Ukraine. In the case of DSTU 7624: 2014 developed and implemented a hardware implementation for multiplication of two polynomials modulo x8+x4+x3+x2+1 in the form of a combinational circuit that allows to execute the MixColumn transformation by one cycle. SubBytes transformation is implemented based on asynchronous read-only memory. For stream cipher, DSTU 8845:2019 the nonlinear function T are implemented as subtitution byte operation in the form of precalculated cells of ROM memory. The multiplication function by α and α-1 in Galois field arithmetic GF (2 64) is realized based on ROM and combinational logic. The control of the modes of operation of the shift register with linear feedback is performed based on a FSM. Both hardware implementations of encryption standards have been verified by the authors according to the specified data in the standard, and their HDL code can be provided by the authors for further research to interested parties.

A lightweight remote attestation using PUFs and hash-based signatures for low-end IoT devices

Remote attestation is a powerful mechanism that allows a verifier to know if the hardware of an IoT (Internet-of-Thing) device (acting as a prover) has been counterfeited or tampered with and if its firmware has been altered. Remote attestation is based on collecting and reporting measurements in a trusted way, and should be lightweight for resource-constrained IoT devices. This work proposes to include a low-cost Root of Trust for Measuring and Reporting (RoTMR) in the prover, based on the combination of a Physically Unclonable Function (PUF) and an Attestation Read-Only Memory (A-ROM), and to use hash-based digital signatures in the attestation protocol. The proposed RoTMR is addressed to IoT devices based on a microcontroller that executes some application code (the measurable object) located in an external non-volatile memory accessible by an attacker. The secret keys required by the digital signatures are not stored but reconstructed using the PUF. The A-ROM contains the attestation instructions and ensures that its contents cannot be altered and that its instructions are executed sequentially without modification. The use of hash-based digital signatures makes the solution quantum-resistant and very robust because its security relies solely on the unidirectionality of a hash function. The proposed attestation protocol takes advantage of the fact that One-Time Signature (OTS) generation and Many-Time Signature (MTS) verification are very well suited for low-end devices, and the MTS scheme is suitable for the verifier application context. The proposal was validated experimentally with the ESP32 microcontroller, which is widely employed in IoT devices, by using its SRAM as PUF and implementing WOTS+, which is a type of Winternitz One-Time Signature scheme (WOTS), the One-Time Signature of Smart Digital Signatures scheme (SDS-OTS), and the MTS schemes constructed with them. The OTS schemes require smaller codes and thus smaller A-ROM than MTS and ECDSA (Elliptic Curve Digital Signature Algorithm). The code of one of the WOTS+ takes about 4 times less space than ECDSA. In terms of execution times, the OTS schemes are very fast. One of the WOTS+ performs all the signature operations in a few tens of milliseconds. The OTS schemes (especially the SDS-OTS) are also very efficient in terms of communication bandwidth because they use small signatures compared to other post-quantum solutions.

What matters for international consumers' choice preferences for smartphones: Evidence from a cross-border ecommerce platform.

Despite the growing impact of smartphone use on countries' economies, the literature has rarely investigated the link between economic context and smartphone purchase trends. Based on 20,556 smartphones sold from a Cross-Border E-Commerce (CBEC) platform, the study reveals that relationships between GDP per capita and Smartphone Choice Preferences (SCP) as well as Purchase Quantities (PUR) are direct and partially mediated by Price (PRI), Read-Only Memory (ROM), and Random-Access Memory (RAM). That means that the economic context highlighted by the GDP plays a substantial role in smartphone choices and purchases. The study suggests that e-sellers and smartphone brands should adapt their marketing and manufacturing strategies to the countries' economic contexts to leverage the fearless competition in the smartphone industry.

Giant electrically tunable magnon transport anisotropy in a van der Waals antiferromagnetic insulator

Anisotropy is a manifestation of lowered symmetry in material systems that have profound fundamental and technological implications. For van der Waals magnets, the two-dimensional (2D) nature greatly enhances the effect of in-plane anisotropy. However, electrical manipulation of such anisotropy as well as demonstration of possible applications remains elusive. In particular, in-situ electrical modulation of anisotropy in spin transport, vital for spintronics applications, has yet to be achieved. Here, we realized giant electrically tunable anisotropy in the transport of second harmonic thermal magnons (SHM) in van der Waals anti-ferromagnetic insulator CrPS4 with the application of modest gate current. Theoretical modeling found that 2D anisotropic spin Seebeck effect is the key to the electrical tunability. Making use of such large and tunable anisotropy, we demonstrated multi-bit read-only memories (ROMs) where information is inscribed by the anisotropy of magnon transport in CrPS4. Our result unveils the potential of anisotropic van der Waals magnons for information storage and processing.