Read-disturb Characteristics Research Articles

Nonvolatile and Voltage-Polarity-Independent Write-Once–Read-Many-Times Memory Feature of an Al/AlOₓ:N/n⁺-Si Device

An aluminum oxynitride (AlO_<i>x</i>:N) resistive memory with a large ON/OFF ratio of 10⁶ at a low read voltage of 0.5 V is proposed. The AlO_<i>x</i>:N resistive switching (RS) layer is fabricated using a two-stage thermal oxynitridation process of an evaporated Al film. The Al/AlO_<i>x</i>: N/n^&#x002B;-Si device shows write-once&#x2013;read-many-times (WORM) characteristics and the writing operation is voltage-polarity-independent. The resistance states can be repeatably read <inline-formula> <tex-math notation="LaTeX">$10^{4}\times $ </tex-math></inline-formula> and the data retention time is over 10⁴ s. A high read-disturb immunity is also observed for over 10⁴ s. Data retention and read-disturb characteristics measured at 85 &#x00B0;C predict a ten-year lifetime of the device. The carrier transport and the RS mechanisms are studied and illustrated.

An Analytical Model of Read-Disturb Failure Time in a Post-Cycling Resistive Switching Memory

We characterize SET/RESET cycling effects on read-disturb failure time in the low resistance state (LRS) of a hafnium-oxide resistive memory cell. We find that the read-disturb failure time degrades by orders of magnitude after SET/RESET cycling. An analytical LRS read-disturb failure time model including cycling induced trap generation rate and its influence on read-disturb characteristics is developed. We compare our read-disturb model with measured results in a wide range of read voltage and SET/RESET cycle number. Good agreement between modeled and measurement results is obtained. We evaluate read-disturb failure time in post-cycling cells for different read failure criteria.

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristics beyond sub-30 nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those of conventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40 nm multi level cell (MLC) NAND device.

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

A new NAND string and its read operation scheme using self-boosting as a solution for improving read disturb characteristics of NAND flash memories are proposed. By using the proposed self-boosting read scheme, which includes an optimized bias voltage and adjusted threshold voltage (Vth) of dummy cells, the self-boosted channel voltage prevents soft-programming in unselected memory cells during read operation due to reduced electric field across tunnel oxide. Compared to the conventional scheme this leads to a significant improvement in read disturb characteristics. From simulation and measurement results, the worst electric field of the proposed NAND flash memory during read operation is decreased by around 50% and Vth shifts caused by read disturb is lowered by around 40%, compared to conventional NAND. The proposed NAND was fabricated in a 60 nm NAND technology and successfully demonstrated.

Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125/spl deg/C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.

Impact of tunnel-oxide nitridation on endurance and read-disturb characteristics of Flash E 2PROM devices

Threshold-voltage window closure in non-volatile memory (NVM) devices is known to originate from charge trapping in the dielectric underneath the floating gate (FG dielectric). In this paper, it is shown that oxide nitridation lowers the generation rate of neutral electron traps and, consequently, reduces the amount of trapped charge. Therefore, FG dielectric nitridation improves the endurance characteristics of NVM devices. Also, write/erase ( W E ) degradation of NVM devices results in a Stress Induced Leakage Current (SILC) through the FG dielectric, enhancing read-disturb. The conduction mechanism of the SILC being trap-assisted tunnelling, FG dielectric nitridation is expected to reduce the SILC. However, the lower trap generation rate in the nitrided oxides is compensated by an enhanced trap-assisted conduction efficiency, resulting in nearly the same SILC as compared to conventional oxides. Therefore, read-disturb is barely affected by nitridation of the FG dielectric.