Abstract
We characterize SET/RESET cycling effects on read-disturb failure time in the low resistance state (LRS) of a hafnium-oxide resistive memory cell. We find that the read-disturb failure time degrades by orders of magnitude after SET/RESET cycling. An analytical LRS read-disturb failure time model including cycling induced trap generation rate and its influence on read-disturb characteristics is developed. We compare our read-disturb model with measured results in a wide range of read voltage and SET/RESET cycle number. Good agreement between modeled and measurement results is obtained. We evaluate read-disturb failure time in post-cycling cells for different read failure criteria.
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