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Exploration of Cultural Teaching Mechanisms of Ideology and Politics Courses under the Background of “Internet Plus”

Abstract As the cradle of cultivating and conveying talents, colleges and universities should innovate the education of ideological and political courses under the background of “Internet+”, focusing on cultivating students’ cultural self-confidence. This paper first explains blockchain-related technology in Internet technology, including the basic principle and structure of blockchain, the consistency Hash algorithm, the consensus mechanism and the credit mechanism of blockchain. Secondly, it discusses the fit between the blockchain and the cultural teaching mechanism of the Civics course, through which blockchain technology can effectively realize the interactive sharing of the cultural teaching resources of the Civics course. Based on the blockchain technology and MVC network structure, an interactive model of cultural teaching resources for Civic and Political Science courses is constructed, which further improves the way students access cultural teaching resources. Finally, a simulation test is conducted to evaluate the interactivity of the cultural teaching resources in the Civics and Political Science course and the effectiveness of the model. The results show that the average write bandwidth of the consistent Hash algorithm is 756.68MBps, and the average read bandwidth is 215.42MBps, and when the total amount of data exceeds 64GB, the relative standard deviation of the Hash algorithm decreases to about 0.15% and remains stable. The cultural teaching mechanism of the Civics course with the introduction of blockchain technology is based on a digital platform, and when the number of network nodes is 150, the delay of the consensus mechanism is 236.73ms, and the throughput reaches about 98 data interactions per second. The cultural teaching mechanism of the Civics and Politics course in the background of the Internet needs to be based on digitization, fully combining with information technology to realize the common construction and sharing of cultural teaching resources and cultivate new-age talents with higher cultural self-confidence for the development of society.

The HSPC — a high speed PCIe readout card for the HFRS-TPC

A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.

Artificial neural networks based predictions towards the auto-tuning and optimization of parallel IO bandwidth in HPC system

Super-computing or HPC clusters are built to provide services to execute computationally complex applications. Generally, these HPC applications involve large scale IO (input/output) processing over the networked parallel file system disks. They are commonly developed on top of the C/C++ based MPI standard library. The HPC clusters MPI–IO performance significantly depends on the particular parameter value configurations, not generally considered when writing the algorithms or programs. Therefore, this leads to poor IO and overall program performance degradation. The IO is mostly left to individual practitioners to be optimised at code level. This usually leads to unexpected consequences due to IO bandwidth degradation which becomes inevitable as the file data scales in size to petabytes. To overcome the poor IO performance, this research paper presents an approach for auto-tuning of the configuration parameters by forecasting the MPI–IO bandwidth via artificial neural networks (ANNs), a machine learning (ML) technique. These parameters are related to MPI–IO library and lustre (parallel) file system. In addition to this, we have identified a number of common configurations out of numerous possibilities, selected in the auto-tuning process of READ/WRITE operations. These configurations caused an overall READ bandwidth improvement of 65.7% with almost 83% test cases improved. In addition, the overall WRITE bandwidth improved by 83% with number of test cases improved by almost 93%. This paper demonstrates that by using auto-tuning parameters via ANNs predictions, this can significantly impact overall IO bandwidth performance.

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

The development of security-aware mobile devices using wide-input–output (IO) nonvolatile memory (NVM) is hindered by high peak current, large area overhead for high read bandwidth (BWR), and considerable energy consumption for data movement between NVM and logic blocks. Furthermore, data stored in NVM are vulnerable to reverse-engineering attacks. This work presents a high BWR security-aware near-memory-computing spin-transfer torque magnetic random-access memory (STT-MRAM) macro using a multi-bit current-mode sense amplifier (MB-CSA) to reduce peak current and energy consumption for wide-IO access, a near-memory shift-and-rotate functionality (NSRF) in conjunction with the MB-CSA to reduce area overhead and enable the completion of read and logic operations within a single cycle, and a reverse-engineering-proof XOR–based memory data protector to protect data stored in NVM against reverse-engineering attacks. A 1-Mb 1024-b read STT-MRAM macro with data protector fabricated using foundry embedded 22-nm STT-MRAM. This work achieved 42.67 GB/s for BWR and 0.23 pJ/b. Inclusion of the NSRF circuit reduced area overhead by 33.3% while increasing latency by only 170 ps.

Distributed deduplication with fingerprint index management model for big data storage in the cloud

As data progressively grows within data centers, the cloud storage models face several issues while storing data and offers abilities needed to shift data in an adequate time frame. This study aims to develop a distributed deduplication model to achieve scalable throughput and capacity utilizing many data servers for duplicating data in parallel with minimal loss. This paper proposes a new cloud storage model based on a distributed deduplication with the fingerprint index management (DDFI) model. The DDFI model operates on three main stages. At the initial stage, the DDFI model makes use of an effective routing technique depending upon the similarity level of the data, which leads to low network overhead by rapid identification of storage locations. In the second stage, the duplicate data identification procedure is carried out by the use of the MD5 algorithm. At the final stage, a fingerprint index management process is executed where a fingerprint index comprises fingerprints and its corresponding position details of every written chunk. For optimizing the results of the deduplication performance, the DDFI model manages the fingerprint index in storage space and only sometimes writes to disk at the same time as the cloud database scheme is idle. The simulation outcome exhibited that the presented DDFI model offered maximum results with a higher deduplication ratio (DR) with a minimum overhead of network bandwidth. From the detailed comparative analysis, it is inferred that the presented DFFI model offered maximum relative DR, maximum duplication performance, minimum read bandwidth, and write bandwidth.

Enhancing the use of Object Based Contents Addressable Storage

In Today's age of Tetra Scale computing, the application has become more data intensive than ever. The increased data volume from applications, in now tackling larger and larger problems, and has fuelled the need for efficient management of this data. In this paper, a technique called Content Addressable Storage or CAS, for managing large volume of data is evaluated. This evaluation focuses on the benefits and demerits of using CAS it focuses, i) improved application performance via lockless and lightweight synchronization ofaccess to shared storage data, ii) improved cache performance, iii) increase in storage capacity and, iv) increase network bandwidth. The presented design of a CAS-Based file store significantly improves the storage performance that provides lightweight lock less user defined consistency semantics. As a result, this file system shows a 28% increase in read bandwidth and 13% increase in write bandwidth, over a popular file system in common use. In this paper the potential benefits of using CAS for a virtual machine are estimated. The study also explains mobility application for active use and public deployment.

Gemini: A Novel Hardware and Software Implementation of High-performance PCIe SSD

In the era of big data, high-bandwidth and high-concurrency architecture of storage systems is urgently needed. Due to the superiority in power consumption, random access rate and shock resistance, NAND flash memory is popularly adopted in enterprise-class storage systems, and gradually takes the place of traditional hard disk. However, this kind of superiority is not off-the-shelf. Several factors, such as out-of-place update and limited erase/program cycles, have hindered the applicability of flash memory in existing storage systems. Therefore, to fully exploit flash memory’s advantages, this paper proposes a high-performance PCIe SSD, Gemini, and depicts its principles in hardware and software implementation. Our proposed Gemini features several hardware and software optimizations, including PBFTL (the page to block mapping FTL), Dysource (a synchronous-interface flash channel controller with the out-of-order scheduling strategy), a customized I/O stack, the scatter/gather DMA and the multi-queue architecture. What’s more, an FPGA-based prototype of Gemini with 2 TB storage capacity is implemented for verification. In experiment, Gemini achieves a maximum read bandwidth of 3.6 GB/s and a maximum write bandwidth of 1.08 GB/s for 64 KB data access. It can also provide remarkable processing rates over 580,000 IOPS and 270,000 IOPS, with regard to 4 KB random read and write respectively.

MARS: Mobile Application Relaunching Speed-Up through Flash-Aware Page Swapping

The approach for fast application relaunching on the current Android system is to cache background applications in memory. This mechanism is limited by the available memory size. In addition, the application state may not be easily recovered. We propose a prototype system, MARS, to enable page swapping and cache more applications. MARS can speed up the application relaunching and restore the application state. As a new page swapping design for optimizing application relaunching, MARS isolates Android runtime Garbage Collection (GC) from page swapping for compatibility and employs several flash-aware techniques for swap-in speedup. Two main components of MARS are page slot allocation and read/write control. Page slot allocation reorganizes page slots in swap area to produce sequential reads and improve the performance of swap-in. Read/Write control addresses the read/write interference issue by reducing concurrent and extra internal writes. Compared to the conventional Linux page swapping, these two components can scale up the read bandwidth up to about 3.8 times. Application tests on a Google Nexus 4 phone show that MARS reduces the launching time of applications by 50 - 80 percent. The modified page swapping mechanism can outperform the conventional Linux page swapping up to four times.

High-Speed Transmission and Mass Data Storage Solutions for Large-Area and Arbitrarily Structured Fabrication through Maskless Lithography

This paper presents the implementation aspects and design of high-speed data transmission in laser direct-writing lithography. With a single field programmable gate array (FPGA) chip, mass data storage management, transmission, and synchronization of each part in real-time were implemented. To store a massive amount of data and transmit data with high bandwidth, a serial advanced technology attachment (SATA) intellectual property (IP) was developed on Xilinx Virtex-6 FPGA. In addition, control of laser beam power, collection of status read back data of the lithography laser through an analog-to-digital converter, and synchronization of the positioning signal were implemented on the same FPGA. A data structure for each unit with a unique exposure dose and other necessary information was established. Results showed that the maximum read bandwidth (240 MB/s) and maximum write bandwidth (200 MB/s) of a single solid-state drive conform to the data transmission requirement. The total amount of data meets the requirement of a large-area diffractive element approximately 102 cm2. The throughput has been greatly improved at meters per second or square centimeter per second. And test results showed that data transmission meets the requirement of the experiment.

(Invited) Resistive Random Access Memory for Storage Class Applications

Resistive RAM (RRAM) is one of the most promising emerging nonvolatile memory technologies thanks to fast operation, superior scalability, low power consumption and potential for 3D stacking. From an architectural point of view, 1T1R architecture is suitable for embedded memory applications while 1S1R based cross-point architecture is suited to high density memory applications. In the 1S1R based cross-point integration, however, the suppression of sneak current paths has been the major technical barrier for the high density RRAM. We show that the sneak path challenge has been overcome by utilizing a Field Assisted Superlinear Threshold (FAST) selector [1]. The FAST selector device uses an insulating amorphous material which provides volatile switching at critical electric field. Excellent selector performance is presented, including high selectivity of > 107, sharp switching slope of < 5mV/dec., and large endurance of > 1011. The low fabrication temperature (≤300°C) of the FAST selector allows 3D stacking of 1S1R memory layers. It is also demonstrated that a volatile switch based selector has inherent benefits such as low voltage overhead for 1S1R integration and high read voltage margin. For the 1S1R demonstration, electrochemical metallization RRAM with a sub-5nm filament is utilized. The RRAM device offers a self-current-limiting feature during the program operation [2]. The self-limited program obviates the need for external current compliance, which can increase the number of concurrent programs in the 1S1R cross-point architecture with reduced power consumption and increased reliability benefits. Furthermore, the hold voltage property (snap-back behavior) of a FAST selector allows novel sensing techniques such as Resistance Ratio Amplification (RRA) which amplifies the intrinsic ON/OFF ratio of RRAM by a factor of > 104 [2]. Besides the direct advantage of increased memory ON/OFF ratio, the RRA technique also reduces BER and increases read bandwidth of the RRAM array. The integrated self-current-limited RRAM with FAST selector enables the high density and high performance 1S1R RRAM technology.

An Approach for the Design of Passive UHF-RFID Tags Mounted on Optical Discs

In this paper, an innovative design strategy for UHF-RFID tags mounted on optical discs (such as DVDs) is presented. By using the metal layer of the disc as the main radiating element, it is possible to overcome the severe limitations of the existing tags for disc identification in terms of read range and bandwidth. The design and synthesis process, based on the proposed circuit model of the tag, is described. A worldwide UHF-RFID tag prototype, for direct mounting on a DVD disc, is designed and fabricated. The measured read range demonstrates that the presented method drastically improves the performance within the whole UHF-RFID band (840-930 MHz), in comparison to the DVD tags found in the available literature.

Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems

Phase-Change Memory (PCM) has emerged as a promising low-power main memory candidate to replace DRAM. The main problems of PCM are that writes are much slower and more power hungry than reads, write bandwidth is much lower than read bandwidth, and limited write endurance. Adding an extra layer of cache, which is logically the last-level cache (LLC), can mitigate the drawbacks of PCM. However, writebacks from the LLC might (a) overwhelm the limited PCM write bandwidth and stall the application, (b) shorten lifetime, and (c) increase energy consumption. Cache partitioning and replacement schemes are important to achieve high throughput for multi-core systems. However, we noted that no existing partitioning and replacement policy takes into account the writeback information. This paper proposes two writeback-aware schemes to manage the LLC for PCM main memory systems. Writeback-aware Cache Partitioning (WCP) is a runtime mechanism that partitions a shared LLC among multiple applications. Unlike past partitioning schemes, our scheme considers the reduction in cache misses as well as writebacks. Write Queue Balancing (WQB) replacement policy manages the cache partition of each application intelligently so that the writebacks are distributed evenly among PCM write queues. In this way, applications rarely stall due to unbalanced PCM write traffic among write queues. Our evaluation shows that WCP and WQB result in, on average, 21% improvement in throughput, 49% reduction in PCM writes, and 14% reduction in energy over a state-of-the-art cache partitioning scheme.

Reducing communication costs in collective I/O in multi-core cluster systems with non-exclusive scheduling

As the number of nodes in high performance computing (HPC) systems increases, collective I/O becomes an important issue and I/O aggregators are the key factors in improving the performance of collective I/O. When an HPC system uses non-exclusive scheduling, a different number of CPU cores per node can be assigned for MPI jobs; thus, I/O aggregators experience a disparity in their workloads and communication costs. Because the communication behaviors are influenced by the sequence of the I/O aggregators and by the number of CPU cores in neighbor nodes, changing the order of the nodes affects the communication costs in collective I/O. There are few studies, however, that seek to incorporate steps to adequately determine the node sequence. In this study, it was found that an inappropriate order of nodes results in an increase in the collective I/O communication costs. In order to address this problem, we propose the use of specific heuristic methods to regulate the node sequence. We also develop a prediction function in order to estimate the MPI-IO performance when using the proposed heuristic functions. The performance measurements indicated that the proposed scheme achieved its goal of preventing the performance degradation of the collective I/O process. For instance, in a multi-core cluster system with the Lustre file system, the read bandwidth of MPI-Tile-IO was improved by 7.61% to 17.21% and the write bandwidth of the benchmark was also increased by 17.05% to 26.49%.

MASSIVELY PARALLEL I/O FOR PARTITIONED SOLVER SYSTEMS

This paper investigates I/O approaches for massively parallel partitioned solver systems. Typically, such systems have synchronized "loops" and write data in a well defined block I/O format consisting of a header and data portion. Our target use for such a parallel I/O subsystem is checkpoint-restart where writing is by far the most common operation and reading typically only happens during either initialization or during a restart operation because of a system failure. We compare four parallel I/O strategies: POSIX File Per Processor (1PFPP), "Poor-Man's" Parallel I/O (PMPIO), a synchronized parallel I/O (syncIO), and a "reduced blocking" strategy (rbIO). Performance tests executed on the Blue Gene/P at Argonne National Laboratory using real CFD solver data from PHASTA (an unstructured grid finite element Navier-Stokes solver) show that the syncIO strategy can achieve a read bandwidth of 47.4 GB/sec and a write bandwidth of 27.5 GB/sec using 128K processors. The "reduced-blocking" rbIO strategy achieves an actual writing performance of 17.8 GB/sec and the perceived writing performance is 166 TB/sec on Blue Gene/P using 128K processors.

ScaleFFS

NAND flash memory has become one of the most popular storage media for mobile multimedia systems. A key issue in designing storage systems for mobile multimedia systems is handling large-capacity storage media and numerous large files with limited resources such as memory. However, existing flash file systems, including JFFS2 and YAFFS in particular, exhibit many limitations in addressing the storage capacity of mobile multimedia systems. In this article, we design and implement a scalable flash file system, called ScaleFFS, for mobile multimedia systems. ScaleFFS is designed to require only a small fixed amount of memory space and to provide fast mount time, even if the file system size grows to more than tens of gigabytes. The measurement results show that ScaleFFS can be instantly mounted regardless of the file system size, while achieving the same write bandwidth and up to 22% higher read bandwidth compared to JFFS2.

Exploiting the replication cache to improve cache read bandwidth cost effectively

Cache bandwidth and reliability are both of great importance for microprocessor design. Recently, the replication cache has been proposed to enhance data cache reliability against soft errors. The replication cache is a small fully associative cache to store the replica(s) for every write to the L1 data cache. In addition to enhancing reliability, this paper proposes to make use of the replication cache in order to improve the performance of multiple-issue superscalar microprocessors by enlarging the cache read bandwidth effectively. Our experimental results show that exploiting a replication cache with only 8 entries can improve the performance of a 4-issue superscalar microprocessor by 9.4% on average without compromising the enhanced data integrity.

An overview of logic architectures inside flash memory devices

In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.

Magnetic films and optics in computer memories

The thermal cycle-time and read bandwidth are calculated for a magnetic film memory which is written by heating from focussed light and read by the same beam at reduced power. The heat flow model approximates the memory bit as a planar disc source and the cycle time T is determined by the condition that, for repetitive writing, the ratio of transient to dc temperature must be >1. Then it is found that the bit radius a must be = thermal diffusion length in time T ( k = thermal diffussivity of substrate); for T s and an Ag substrate this gives a \sim 5 \mu . For a magneto-optical reflection coefficient k \sim 10^{-3} the shot-noise limited bandwidth is then found to be ∼100 MHz for a temperature rise of 10 degrees in the memory bit. Surface noise due to imperfections will limit the bandwidth to less than the shot-noise limit unless some form of signal processing can be used to extract the magnetic information. For incident light polarized at, say, 45° to the plane of incidence, phase modulation of one of the components will generate a magneto-optical signal with a phase of 0 or π relative to the modulation, depending on the magnetic state of the memory bit. Additional topics which are considered include a review of magneto-optical enhancement using multilayer dielectric films, a discussion of possible memory materials, and a proposal for a content-addressed memory which is interrogated magneto-optically.