Rapid Thermal Annealing Cycles Research Articles

Reduction in threading dislocation density in ge epitaxial layers grown on Si(001) substrates by using rapid thermal annealing

We investigated the effects of RTA (rapid thermal annealing) on Ge epitaxial layers grown on Si(001) substrates. We found that a high RTA temperature of up to 800 °C was more effective in reducing the threading dislocation density (TDD) in the Ge layer because dislocations with higher velocities were more easily annihilated with each other at higher temperatures. We also found that the TDD was reduced by using RTA at 800 °C, leading to improved crystallinity. As the number of RTA cycles was increased to 20, the TDD was further lowered to 3.5 × 107 cm−2. Moreover, the growth of GaAs on Ge/Si that had been RTA annealed ten times showed improved crystallinity and optical property.

The geometry of catastrophic fracture during high temperature processing of silicon

The geometry of fracture associated with the propagation of cracks originating at the edges of (001) oriented, 200 mm diameter silicon wafers has been investigated under two regimes of high temperature processing. Under spike annealing, fracture did not occur on low index planes and all except one wafer exhibited crack patterns that started initially to run radially, but after a distance of typically 20–30 mm, turned and ran almost tangentially. Wafers subjected to plateau annealing, with a 60 s dwell time at high temperature, predominantly fractured through radial cracks running along $$\langle 110\rangle $$ directions. X-ray diffraction imaging reveals substantial slip in all wafers subjected to plateau annealing. We demonstrate using finite element (FE) modelling that the change in fracture geometry is associated with this plastic deformation, which changes the stress distribution during the cooling phase of the rapid thermal annealing cycle. FE simulations without plastic relaxation show that the radial component of the thermal stress distribution is compressive in the centre of the wafer, causing the crack to run tangentially. Simulations incorporating temperature dependent plasticity showed that the equivalent stress becomes tensile when the plateau anneal allows time for significant plastic relaxation, permitting the crack to continue propagating linearly.

Cathodoluminescence investigations of GaInNAs on GaAs(111)B

In this work, we present a detailed cathodoluminescence characterization of GaInNAs quantum wells grown on GaAs(111)B. As-grown and annealed InGaAs and GaInNAs quantum wells were maeasured and compared by spatially resolved cathodoluminescence at different photon energies. In the case of GaInNAs quantum wells, an increase of the luminescence intensity, a blueshift, and an increment of the modulation depth of intensity profiles were found after rapid thermal annealing cycles. The latter is caused by the presence of nonradiative areas above the GaInNAs quantum well due to stacking faults formed during the growth.

MBE growth and processing of diluted nitride quantum well lasers on GaAs (1 1 1)B

We have grown by Molecular Beam Epitaxy GaInNAs/GaAs (1 1 1)B quantum wells (QWs) embedded in p-i-n diode and laser diode structures. The impact of the different growth parameters (As flux, growth temperature, growth rate, ion density) on the optical and structural properties of this material is studied by Photoluminescence and Atomic Force Microscopy. Additionally, systematic studies of rapid thermal annealing cycles have been performed to optimize the laser structures. Finally, edge-emitting laser diodes have been processed using these structures. These devices showed room-temperature laser emission above 1.2 μm under pulsed current conditions.

Boron Profile Narrowing in Laser-Processed Silicon after Rapid Thermal Anneal

The narrowing or broadening of the boron profile during annealing of laser-processed samples is observed to occur depending on which of two competing mechanisms, uphill diffusion of boron due to a highly defective single-crystal layer near the surface or transient-enhanced diffusion due to end-of-range defects, dominates during the post-laser processing anneal. The results show that uphill diffusion of boron is found to dominate during annealing of a single-pulse laser-processed sample because the defects near the surface cannot be efficiently removed with a single laser pulse adjusted to a value that can melt the amorphous silicon but not the underlying crystalline substrate. Junctions thus become shallower with the post-laser processing anneal. However, with successive laser pulses, the dopants are observed to move deeper into the silicon with subsequent rapid thermal annealing cycles. This could be due to the reduced contribution of uphill boron diffusion when the defects near the surface decrease with successive pulses. The end-of-range defects, which cannot be sufficiently annealed because the melt depth is not beyond the amorphous layer, thus play the key role in broadening the boron concentration profile for multiple-pulse laser-annealed silicon. © 2003 The Electrochemical Society. All rights reserved.

Effect of Crystal Orientation on Dielectric Properties of Lead Zirconium Titanate Thin Films Prepared by Reactive RF-Sputtering

Theoretical calculations based on phenomenology of ferroelectrics have been previously reported for lead zirconium titanate (PZT) system. This paper offers an experimental comparison of the crystal orientation dependence of dielectric properties for PZT thin films grown using reactive RF-sputtering. Highly oriented PZT thin films with a rhombohedral composition have been grown in different orientations using selective rapid thermal annealing cycles. The PZT(100) oriented films showed larger dielectric constant and loss compared to PZT(111) films. The PZT(100) films possessed sharp square-like hysteresis loops indicating a instantaneous switching of domains at the coercive field whereas the PZT(111) films showed smooth hysteresis loops as expected from our phenomenological calculations.

Dielectric Properties of Highly Oriented Lead Zirconium Titanate Thin Films Prepared by Reactive RF-Sputtering

AbstractHighly (100) and (111) oriented lead zirconium titanate (PZT) thin films have been grown by using reactive rf-sputtering. PZT thin films with rhombohedral composition have been grown in different orientations using selective rapid thermal annealing cycles. The polarization versus electric field curves and the resistivity of the films were measured using a standardized RT66A ferroelectric test system. The dielectric constant and the loss were determined using an impedence analyzer. The PZT(100) oriented films showed larger dielectric constant and loss than the PZT(111) films. The PZT(100) films possessed sharper square-like hysteresis loops compared to the PZT(111) films, as expected from our phenomenological calculations.

Arsenic precipitation from thin surface layers of low-temperature grown GaAs

Arsenic precipitation from a thin, 100-nm surface layer of GaAs grown at low temperature (LT) by molecular beam epitaxy is investigated. The precipitate depth distribution is examined for different rapid thermal annealing cycles. It is found that the precipitate distribution can tail a long distance into the underlying stoichiometric GaAs layer, depending on the peak annealing temperature. The distribution for an 800 °C anneal is virtually unaffected by a prior low temperature ‘‘soak’’ at 600 °C, thus showing that the precipitation is insensitive to the initial point defect concentrations in this temperature range. The relevance of these results to the precipitation process and to the use of thin LT layers in device applications is discussed.

Electrical and optical characterisation of silicon and silicon/phosphorus implantsin InP doped with iron

AbstractSilicon implantations into semi-insulating InP with a wide range of doses and energies have been carried out with the aim of obtaining n type layers suitable for device applications. The electrical activations obtained were typically about 70%, reaching 80% for Si/P co-implants with a dose of 1014 cm−2, and the electrical depth profiles showed no redistribution of the implants during annealing. The mobilities obtained after all rapid thermal annealing cycles used were very high, indicating the good crystalline quality of the resulting layers. This was confirmed by Raman scattering measurements, which showed that even if the material is completely amorphised by the implantation, the annealing treatment restores the emissions found for as received unimplanted InP. After Si implantation, the photoluminescence spectrum of the samples showed the appearance of a band at 1·17 eV with high thermal stability, the origin of which was tentatively assigned to Vp–Sip (P vacancy–Si on P lattice site) complexes....

Thermally stable WTiAu non-alloyed ohmic contacts on In 0.5Ga 0.5As for GaAsAlGaAs heterojunction bipolar transistor applications

This paper demonstrates WTiAu as a thermally stable, low resistance, non-alloyed, emitter ohmic contact for GaAsAlGaAs heterojunction bipolar transistor applications. The minimum W layer thickness required for low contact resistance and long-term thermal stability was obtained. A W layer 900 Å thick yielded the lowest contact resistance ( R c = 0.045 ω mm ) with a high degree of uniformity after (1) a collector ohmic contact rapid thermal annealing cycle at 420 °C and (2) 500 h at 250 °C. Secondary ion mass spectroscopy results indicate that In outdiffusion contributes to the thermal instability when thinner W layers are used.

Reduced Thermal Budget Borophosphosilicate Glass (BPSG) Fusion and Implant Activation Using Rapid Thermal Annealing and Steam Reflow

ABSTRACTHighly dense next generation dynamic random access memory (DRAM) devices impose severe restrictions on the times, temperatures and atmospheres of all thermal process steps following the sourcedrain implantation. BPSG reflow and source-drain implant activation are two of the process steps that contribute significantly towards enhanced overall thermal budget during the fabrication of DRAM devices.In this paper, we present the results of an optimized thermal budget process using a combination of steam reflow and rapid thermal annealing (RTA). We demonstrate that this approach produces better reflow characteristics than the best RTA or reflow cycle alone. The processes will be compared on pchannel CMOS devices and the differences in various electrical characteristics will be highlighted. The results of BPSG reflow and dopant outdiffusion will be presented. Experimentally obtained data on junction depth from SIMS analysis will be correlated with corresponding RTA simulation results.

Annealing and activation of Si implanted InP

The recovery of implant damage, and the activation of Si implanted into InP has been studied over a range of post-implant anneal temperatures from 295 to 1095 K. 600 keV Si+ ions were implanted to doses ranging from 3.6 × 1011 to 2 × 1014 cm−2, and the resultant damage monitored by the Rutherford backscattering/channeling technique. For InP(Zn) and InP(S) wafers of (100) orientation, and undoped metalorganic chemical vapor deposition epilayers grown on InP(Fe) semi-insulating substrates, spontaneous recovery of lattice damage occurs at 295 K. For Si doses ≤ 4 × 1013 cm−2, up to 70% of the initial damage (displaced atoms) annealed out over a period of ≊85 days. The degree of recovery was found to depend on the initial level of damage. Recovery is characterized by at least two time constants; t1 < 5 days and t2 ≊ 100 days. Anneal rates observed between 295 and 375 K are consistent with an activation energy of 1.2 eV. Hall effect measurements following rapid thermal annealing of implanted epilayers, indicate that electrical activation commences at about 850 K; full activation is achieved by 1045 K, this process being characterized by an activation energy of 1.9 eV. The room temperature photoluminescence intensity, which remains almost constant for the unimplanted epitaxial InP over the full rapid thermal annealing (RTA) range, is extinguished after implantation and only recovers to about 18% of the value for the unimplanted reference material. This appears to be associated with the appearance of thermal etch pits which are most pronounced at the highest RTA temperatures and the higher implant doses. These etch pits are almost absent in the unimplanted material subjected to the same RTA cycles.

Low-Resistivity Amorphous Silicon for Contacts Using Low-Temperature Rapid Thermal Annealing

ABSTRACTFabrication of SiGe heterojunction bipolar transistors (HBTs) requires a low thermal budget to avoid relaxation of the strained SiGe base layer. Ion implantation is one of the most widely used techniques to achieve contacts. However, due to thermal budget constraints, low temperature rapid thermal annealing (RTA) cycles to activate these implants are insufficient to anneal out all of the implant damage. Polysilicon contacts provide an alternative to ion implantation, but are typically annealed at high temperatures (>950°C) to achieve low sheet resistivity. In this study, amorphous silicon and polycrystalline silicon films were implanted with boron, arsenic, or phosphorus and RTA'd at temperatures from 800°C to 950°C and compared to single crystal silicon with identical implants and RTA cycles. The films were characterized using four-point probe, Hall measurements, TEM (transmission electron microscopy), and SIMS (secondary-ion mass-spectrometry). TEM analysis shows that the amorphous deposition produces larger grains upon RTA due to more rapid grain growth than the polycrystalline deposition. The sheet resistance for the amorphous deposited films is much lower than that of the polycrystalline deposition for all implant conditions. Activations of the implants indicate that the arsenic and phosphorus segregate to the grain boundaries, while the boron does not. The segregation is more significant for the polycrystalline films than for the amorphous films and can be explained by the grain boundary area. For contacts to the SiGe HBT, which requires a low thermal budget, an amorphous deposited silicon film is advantageous over a polycrystalline film at low annealing temperatures because it has lower sheet resistance, less segregation to the grain boundaries, and produces larger grains.

Grain Growth in Al-2% Cu Thin Films

The grain size and grain growth kinetics in sputter deposited Al-2% Cu films on silicon substrates were determined by TEM for various film thicknesses and anneal times, temperatures and methods. Grain sizes were found to be typically lognormally distributed. The as- deposited grain size (d{sub o}) dependence on film thickness (TH) was found to be d{sub o} = C TH{sup {1/2}}, due to competitive grain growth during film formation. Annealed grain size (d) after Rapid Thermal Annealing (RTA) for time (t) at temperature (T) is described by the general equation d {minus} do = C TH{sup 0.7} {l brace}t exp ({minus}{Delta}E{sub a}/kT){r brace}{sup 1/8}, where {Delta}E{sub a} = 0.85 ev for 0.4 {mu}m films and {Delta}E{sub a} = 1.1 ev for 0.8 {mu}m films. Grain growth is largely saturated for these anneals. Grain growth is shown to be more extensive during RTA anneals than furnace annealing and more extensive in 0.4 {mu}m films than 0.8 {mu}m films for equivalent RTA cycles. The results are discussed in terms of models, simulations and previous results of grain growth in thin metal films. 21 refs., 4 figs.

Rapid thermal annealing of YBaCuO thin films sputtered on [formula omitted] substrates

We have determined the rapid thermal annealing (RTA) conditions that optimize both the surface quality and the superconducting properties of YBaCuO films deposited on silicon-based substrates. This process has allowed a very thin nitride layer (45Å) to be a good diffusion barrier; silica acting as a sticking layer. A T(onset) in the 87–91 K range has been obtained, with T( R = 0) ∼- 60 K and Jc ∼- 500 A.cm −2 at T(R = 0) 2 . Repeated RTA cycles might by a way to improve these figures.

Detection of surface accumulation of dopants in rapid-thermally-annealed, shallow-implant silicon

Rapid thermal annealing (RTA) of ion-implanted silicon is a procedure for annealing the damage caused by implantation while minimizing the redistribution of the implanted dopant species. The accumulation of dopant atoms at interfaces and at the surface as a result of the annealing can have significant effects on the electrical properties of the material. We have studied the surface accumulation of B and Sb implanted at low energy into silicon (with a subsequent RTA cycle) by using low-energy ion scattering, nuclear reaction analysis, and Rutherford backscattering. The use of these complementary techniques has enabled the confirmation of the presence of surface accumulation of dopant material in each case. Each technique leads to different specific information.

Characterization of n-type regions in GaAs formed by silicon fluoride molecular ion implantations

Implantations of silicon and silicon fluoride ions into semi-insulating GaAs wafers were performed to compare and evaluate the quality of the n-type layers that were produced. The use of SiFx (x=1,2,3) molecular ion implantations creates n-type active regions and n+ ohmic contact layers employing a higher implant energy than that needed to achieve a similar projected range for silicon ions. The higher energy allows the implanter to operate with a more stable and reproducible ion beam for shallow implant applications. Variables affecting the net electrically active ion distributions, such as the ion beam incidence angle, and the use of furnace or rapid thermal annealing cycles for implantation activation are addressed. Capacitance-voltage profiles were obtained for the n-type regions, and the free carrier distributions for the n+ implantations were obtained by polaron electrolytic profiling. The implanted regions were characterized by Hall-effect measurements, cathodoluminescence, and secondary ion mass spectroscopy.

LPCVD of silicon dioxide by pyrolysis of teos in a rapid thermal processor

Low-pressure chemical vapor deposition of SiO 2 by pyrolysis of tetraethylorthosilicate (TEOS), in a lamp-heated, cold-wall rapid thermal processor has been investigated. Effects of rapid-thermal and furnace annealing on the chemical and electrical properties have been studied using standard etching and C- V techniques. Our results have shown that silicon dioxide can be deposited at rates as high as 1000 Å/min. Below 800°C, the deposition process is limited by the surface reactions and has an activation energy of 76 kcal/mol. Silicon dioxide films very close to thermal oxide in density can be obtained by following the deposition with a standard furnace or rapid thermal annealing cycle in a nitrogen ambient. The fixed interface charge density of the deposited films is higher than that of a dry oxide control sample processed under the same conditions. The charge densities range from 6.4 × 10 11 to 8.8 × 10 11 cm −2 for furnace annealed films and from 1.58 × 10 11 to 3.72 × 10 11 cm −2 for rapid thermally annealed films.

Polycrystalline Silicon Emitter Contacts Formed by Rapid Thermal Annealing

The effect of rapid thermal annealing on the formation of polycrystalline silicon/interfacial oxide/single crystal silicon emitters is examined. The emitter width, defined as the distance from the oxide to the emitter junction, and the base width, defined as the distance from the emitter to the base junction, are measured by secondary ion mass spectrometry and spreading resistance depth profiling, thus differentiating between metallurgical and electrical junctions. Under isochronal annealing conditions of 10s, the metallurgically‐electrically equivalent emitter width increases monotonically from 0.04 μm at 900°C to 0.11 μm at 1050°C. By contrast, the nominal 0.38 μm metallurgical and 0.14 μm electrical base widths are essentially invariant to temperature. Under isothermal annealing conditions of 1050° and 900°C, there is almost no dependence on time of the emitter and base widths from 1 to 10, and 10 to 30s, respectively. Arsenic diffuses out of the polycrystalline silicon under all annealing conditions, especially as the annealing temperature is raised, causing an increase in sheet resistance of the emitter that is partly proportional to the arsenic loss. High resolution transmission electron microscopy shows that the interfacial oxide layer is stable to at least 900°C with both the number and size of epitaxial protuberances increasing with temperature, but not with annealing time. At 1050°C the interfacial oxide layer agglomerates, and as a consequence, epitaxial realignment of the polycrystalline silicon grains with the single crystal substrate occurs. By comparison, 30 min furnace annealing at 950°C results in emitter and base widths of 0.10 and 0.30 μm, respectively. There is almost no loss of arsenic, and the emitter sheet resistance is almost three times lower, and the base pinch resistance is approximately four times higher than that obtained by any rapid thermal annealing cycle. The interfacial oxide, although bumpy, remains intact, thus preventing any epitaxial realignment from occurring.

Channeling and nuclear reaction analysis of shallow B- and BF2- implanted Si

Ion channeling and nuclear reaction analysis (NRA) have been used to study rapid thermal annealing (RTA) of 10-keV B- and 45-keV BF2-implanted, crystalline, and preamorphized Si. Samples were capped with SiO2 and annealed in a nitrogen atmosphere with an AG Associates 210T Heatpulse system. Damage depth distributions were determined with He+ ion channeling. Extensive disorder was observed near the B projected range following a 1050 °C/20-s RTA cycle of B-implanted crystalline Si. For the same annealing conditions, much less residual damage was apparent for B-implanted preamorphized Si. No disorder was observed in the near-surface region (<30 nm) following a 1050 °C/20-s RTA cycle of BF2-implanted, crystalline, and preamorphized Si. Post-anneal damage at the original amorphous/crystalline interface was greater for BF2-implanted crystalline Si compared to BF2-implanted preamorphized Si. The relative retained B and F doses were determined with NRA using the 11B(p,α)8Be* and 19F(p,α0)16O reactions, respectively. A significant loss of B was observed following RTA of BF2-implanted preamorphized Si. No loss of B was apparent for all other annealed samples. A loss of F was observed for all annealed samples. For identical annealing conditions, the relative retained F dose of BF2-implanted preamorphized Si was less than that of BF2-implanted crystalline Si.