RSFQ Research Articles

High performance rapid single-flux-quantum bit-slice arithmetic logic unit

Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm2 Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 × 0.81 mm2. All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100% utilization rate, regardless of carry/borrow read-after-write correlations between instructions.

Quantum thermodynamics with a single superconducting vortex.

We demonstrate complete control over dynamics of a single superconducting vortex in a nanostructure, which we coin the Single Vortex Box. Our device allows us to trap the vortex in a field-cooled aluminum nanosquare and expel it on demand with a nanosecond pulse of electrical current. Using the time-resolving nanothermometry we measure [Formula: see text] joules as the amount of the dissipated heat in the elementary process of the single-vortex expulsion. Our experiment enlightens the thermodynamics of the absorption process in the superconducting nanowire single-photon detectors, in which vortices are perceived to be essential for a formation of a detectable hotspot. The demonstrated opportunity to manipulate a single superconducting vortex reliably in a confined geometry comprises a proof of concept of a nanoscale nonvolatile memory cell with subnanosecond write and read operations, which offers compatibility with quantum processors based either on superconducting qubits or on rapid single-flux quantum circuits.

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

Simulations of superconducting quantum gates by digital flux tuner for qubits

Abstract The interconnection bottleneck caused by limitations of cable number, inner space and cooling power of dilution refrigerators has been an outstanding challenge for building scalable superconducting quantum computers with the increasing number of qubits in quantum processors. To surmount such an obstacle, it is desirable to integrate qubits with quantum–classical interface (QCI) circuits based on rapid single flux quantum (RSFQ) circuits. In this work, a digital flux tuner for qubits (DFTQ) is proposed for manipulating flux of qubits as a crucial part of the interface circuit. A schematic diagram of the DFTQ is presented, consisting of a coarse tuning unit and a fine-tuning unit for providing magnetic flux with different precision to qubits. The method of using DFTQ to provide flux for gate operations is discussed from the optimization of circuit design and input signal. To verify the effectiveness of the method, simulations of a single DFTQ and quantum gates including a Z gate and an iSWAP gate with DFTQs are performed for flux-tunable transmons. The quantum process tomography corresponding to the two gates is also carried out to analyze the sources of gate error. The results of tomography show that the gate fidelities independent of the initial states of the Z gate and the iSWAP gate are 99.935% and 99.676%, respectively. With DFTQs inside, the QCI would be a powerful tool for building large-scale quantum computers.

Research on the current compensation mechanism of FJTL in ERSFQ

Energy-efficient rapid single flux quantum (ERSFQ) devices have unique energy advantages with a power consumption of less than 0.001fJ per single-bit switch, even considering the energy required for the refrigeration system, achieving ultra-low energy consumption of sub-fJ/bit. Combined with its typical operating frequency in the tens of GHz range, ERSFQ circuits have the potential to realize computing chips with extremely high computational power and energy efficiency, making them highly promising for applications in the post-Moore era. However, the performance improvement of ERSFQ circuits faces two challenges. One is how to reduce the size of their feeding Josephson transmission line (FJTL), which is required to stabilize the voltage bias of the ERSFQ circuits. The second challenge is how to improve their bias margin. The measured bias margin of ERSFQ circuits is relatively smaller than for Rapid Single Flux Quantum (RSFQ) circuits. This study investigates the current compensation mechanism of the FJTL and derives a formula for the compensating current ΔI in the main logic circuit by each pulse input to the FJTL. Based on the formula, a method is proposed to enhance the bias margin of ERSFQ circuits while reducing the size of FJTL by applying feeding pulses into the FJTL. We applied this method to an 8-bit ERSFQ shift register (SR), where the size of its FJTL is 4 JTLs (each JTL consists of 2 Josephson junctions). The measurement demonstrated an improvement of the bias margin from [84 %, 104 %] to [38 %, 104 %], confirming the feasibility of the proposed method. Furthermore, by comparing the measurement results of an 8-bit ERSFQ SR, where the size of its FJTL is 6 JTLs, it is demonstrated that applying this method can also reduce the size of the FJTL while maintaining a large margin.

Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.

Side-Channel Leakage in SFQ Circuits and Related Attacks on Qubit Control and Readout Systems

Single flux quantum (SFQ) technology is currently used as a cryogenic control and readout circuitry of superconducting quantum computers. The low power operation and high switching frequency of SFQ technology are instrumental to efficiently scale a quantum computer. With the growing interest in the hardware security of SFQ circuits, a novel side-channel leakage mechanism in SFQ-to-DC converters is uncovered in this paper. The leakage mechanism is investigated for two logic styles, namely rapid SFQ (RSFQ) and energy-efficient RSFQ (ERSFQ). By observing the fluctuations in the power supply provided by the room temperature electronics, a malicious adversary can extract critical information about the applied input signals. This type of side-channel leakage can lead to serious security vulnerabilities for superconducting electronics and quantum computers. Two potential side-channel attacks that exploit this vulnerability and target SFQ-based qubit control and readout systems are proposed.

Timing Regulation Scheme for RSFQ Circuit

Rapid single-flux-quantum (RSFQ) circuit requires an accurate timing scheme to maintain correct function, especially under a very high clock frequency. However, the reported timing regulation schemes have issues, including the bias margin of the circuit being small and the bias margin decrement caused by imprecise timing constraints. This paper proposes a new timing regulation scheme based on clock-follow-data clocking that can solve the problems. The scheme uses the unique structure of the RSFQ circuit to eliminate the impact caused by different timing libraries and extend the biasing margin. The simulation results of the XOR gate under various timing regulation schemes demonstrated that the proposed scheme could obtain the maximum STA bias margin. Also, the STA bias margin of the 4-bit parallel arithmetic logic unit (ALU) designed using the timing regulation scheme proposed in this paper was increased by 5%, the PSCAN2 bias margin was increased by 7.4%, and 36 ps reduced latency. The ALU fabricated using the “SIMIT Nb03” process was successfully measured with correct operation at low frequency. It showed this scheme could provide accurate timing constraints range and enhances circuit bias margin.

Design of Passive Transmission Line by Adjusting Intrinsic Parameters of Josephson Junctions

Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum (RSFQ) circuits by adjusting the Stewart McCumber parameter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\beta_c$</tex-math></inline-formula> of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from the JJ's modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\beta_c$</tex-math></inline-formula> on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. ±30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.

Energy efficient half-flux-quantum circuit aiming at milli-kelvin stage operation

Half-flux-quantum (HFQ) circuits are based on 0–π superconducting quantum interference devices (SQUIDs) and is one of the energy-efficient superconductor digital circuits. The bit energy is determined by the critical current I cn of 0–π SQUID, which can be easily tuned with the loop inductance and junction critical current. In this work, an alternative π–π–π SQUID is adopted to demonstrate HFQ circuits to simplify the fabrication process and enhance circuit energy efficiency. The properties of superconductor/ferromagnet/insulator/superconductor Josephson junctions (π-JJs) are measured with temperature dependence from 4.2 K down to 10 mK. HFQ toggle flip-flops (TFFs) are successfully demonstrated at frequencies of up to 6.7 GHz and 44.5 GHz at temperatures of 4.2 K and 10 mK, respectively. Comparing the HFQ TFF with its rapid single-flux quantum counterpart under the same fabrication process, it is anticipated that the HFQ TFF will exhibit approximately 70% reduction in both static and dynamic energy dissipation. This research establishes the foundation for developing cryogenic interface control and readout circuits for large-scale quantum computing in the future.

Striking a Good Balance Between Area and Throughput of RSFQ Circuits Containing Feedback Loops

Electronic design automation solutions are being developed to support the synthesis and physical design optimization of Rapid Single Flux Quantum (RSFQ) logic circuits with hundreds of thousands of logic cells. The clocked feature of synchronous RSFQ cells results in gate-level pipelined designs, requiring a large number of path-balancing D-flipflops (DFFs). In addition, one also faces the challenge of maintaining high throughput for RSFQ circuits containing feedback loops. To enforce the coincidence of the input and feedback patterns, one can apply a new input pattern every <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L$</tex-math></inline-formula> cycles, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L$</tex-math></inline-formula> is the length of the feedback loop. Consequently, the throughput of circuits with feedback loops is only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1/L$</tex-math></inline-formula> of the clock frequency. In this paper, we present two methods to improve the performance and area of RSFQ circuits, especially targeting circuits with feedback loops: (i) An area-oriented optimization method that removes the path-balancing DFFs by capturing and repeating input patterns. (ii) A throughput-oriented optimization method that enables an RSFQ circuit to receive and correctly process an input pattern every clock cycle. For a large circuit such as S526 in the ISCAS89 benchmark circuits, the circuit can initially receive an input pattern only every 9 cycles. As a result of applying our area-oriented optimization, the circuit admits 33% fewer logic cells while receiving input patterns every 11 cycles. Alternatively, our throughput-oriented optimization yields a circuit that can receive new input patterns on every cycle with nearly the same cell count.

Demonstration of Interface Circuits for Adiabatic Quantum-Flux-Parametron Cell Library Using an Eight-Metal Layer Superconductor Process

In this paper, we designed and demonstrated interface circuits between AQFP (adiabatic quantum-flux-parametron) and RSFQ (rapid single-flux-quantum) circuits according to the established AQFP and RSFQ cell libraries using the MIT LL SFQ5ee process. The principles of these interfaces are based on ones that were previously designed and demonstrated using a four-metal-layer superconductor process. The AQFP-to-RSFQ interface is based on an RSFQ comparator, where an output current from an AQFP buffer is converted to an SFQ pulse output. The RSFQ-to-AQFP interface is based on an RSFQ D flip-flop, where the internal state of the D flip-flop is read out by an AQFP buffer. Thanks to the eight-metal-layer process, the interfaces can be designed with reduced circuit area compared to original designs with the four-metal-layer process. We designed, fabricated, and tested an AQFP-RSFQ hybrid multiplexer test circuit as an example of utilization of the interfaces, which results in correct operation with reasonably wide bias margins in low-frequency tests.

Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits

This paper proposes a fast automatic gate placement method for gate-level-pipelined Rapid Single Flux Quantum (RSFQ) circuits that are designed to have a high throughput. In such circuits, the gates in a pipeline stage are placed in a column and wires are routed in the area between adjacent columns. In wire routing, wire length-matching is performed. The proposed method performs gate placement for a given netlist to minimize the sum of the maximum distance between connected gates in each pair of adjacent columns. It leads to short wire extensions in wire length matching for increasing the operation frequency and small circuit area. The proposed method consists of a recursive procedure including two placements, selecting a pivot column, and determining the gate placement in the pivot column. The netlist is divided into two netlists with the pivot column. The recursive procedure performs gate placements for the two divided netlist. It is repeated until the location of every gate is determined. We implemented a placement tool by the proposed method and performed the gate placement for three circuits including several hundreds of gates. The proposed placement was 14 to 40 times faster than a placement based on simulated annealing where the sum of the maximum distance between connected gates is approximately the same.

Superconducting-Oscillatory Neural Network With Pixel Error Detection for Image Recognition

Brain-inspired oscillatory neural networks (ONNs) utilize coupled oscillators to emulate biological neuronal dynamics. ONNs are naturally suitable for image/pattern recognition. Many hardware implementations of ONNs have been explored recently by using analog or digital CMOS systems, which can be limited by Moore's law. In this work, we used one of the advanced superconducting technologies for coupled oscillator networks to further improve the energy efficiency and processing speed. Inductively coupled ring oscillators using rapid single flux quantum (RSFQ) technology were designed and simulated. These Josephson junction (JJ) based oscillators can operate as fast as tens of GHz but only consume a energy of several aJ per operation. Excluding cryo-cooling factors, the estimated power consumption of our RSFQ oscillator is hundreds of nW at a frequency of 12.5 GHz, which is multiple times smaller than a typical CMOS ring oscillator. Furthermore, a system for pattern recognition with error detection was designed based on these oscillators. Synchronization dynamics in a pair of coupled oscillators were used to identify whether a test pixel matches a reference pixel. A network comprised of 16 pairs of oscillators were wired together, along with synchronization detectors and a fluxon integrator to demonstrate pattern recognition function. This work was performed using standard JJ models and demonstrated through WRspice and JoSIM software simulations. The circuits and systems proposed in this work aim to provide insights into the use of superconducting technology for implementing ONNs and may serve as basic building blocks for the design of more complex oscillatory computational networks in image processing and beyond. Single oscillator modeling and systematic network function exploration will be performed in future work.

Adopting a Standard Track Routing Architecture for Next-Generation Hybrid AC/DC-Biased Logic Circuits

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

Demonstration and Comparison of On-Chip High-Frequency Test Methods for RSFQ Circuits

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

60-GHz Single Flux Quantum Pulse Transfer Circuit for Serial Biasing

Serial Biasing (SB) is a technique to reduce the total DC bias current of Rapid Single Flux Quantum (RSFQ) circuits by partitioning a design into several islands with isolated grounds and sequential biasing. In this paper we focus on the design of a driver-receiver pair (DRP) to transfer pulses between islands that are galvanically isolated for pulse streams. We discuss both DRP itself and the structure for its testing, that comprises several DRPs connected in series, on-chip pseudo random binary sequence (PRBS) generator for circuit stimulation, and HF output interface. We use the layout of DRPs’ chain as an example to illustrate the advantage of the grapevine (GV) approach, introduced earlier, to manage the bias current flowing into and out of an island. The GV current management technique is analyzed by both electromagnetic simulations and measurement, compared, and contrasted with the so-called ‘straightforward’ (SF) approach. The maximum operational frequency for SF test structure was 10 GHz with zero margins for the SB current. Measurements of the GV structure at 10 GHz demonstrated BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> with ±5.8% margins for SB current. We observed the correct operation of the 5-island DRP chain up to 60 GHz using the grapevine approach for SB current management. All chips were fabricated at MIT Lincoln Laboratory using SFQ5ee fab node.

$\upalpha$-Soma: Single Flux Quantum Threshold Cell for Spiking Neural Network Implementations

The main challenge for the hardware implementation of spiking neural networks is the design of a reliable neuron. Soma, which is the nucleus of the neuron, is a key part of such a design. More precisely, the soma design must accurately capture the excitatory/inhibitory interactions, intrinsic charge dynamics, refractory period, spike encoding, neuronal action potential, and output spike firing processes in order to mimic the corresponding biological processes. This work presents the design of an artificial soma cell with excitatory and inhibitory inputs, called <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\alpha$</tex-math></inline-formula> -Soma. The key idea is to design and employ a new interconnect cell, named <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\alpha$</tex-math></inline-formula> -cell, and integrate this cell within the proposed soma cell design. The design implementation utilizes the Rapid Single Flux Quantum (RSFQ) logic circuit technology. We demonstrate the correct functionality, high performance, and energy efficiency of the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\alpha$</tex-math></inline-formula> -Soma cell with detailed circuit simulations under different spiking conditions.

Optimization and Verification of RSFQ and AQFP Logic Circuits Using JoSIM Tools

Various techniques exist to optimize functioning RSFQ circuits for improved critical margins. Existing techniques generally employ a center of gravity method. We present the additional use of a minimal distance to failure optimization technique through the ad-hoc tools for the superconducting circuit simulation engine JoSIM. These techniques are used to optimize the margins of RSFQ circuits through verification of Josephson junction phase. This verification method is extended to incorporate the output current in an attempt to optimize the highly energy efficient AQFP logic family. Results are presented for pre and post optimized logic circuits for both families.

Power Optimization of 50 GHz ERSFQ Circuits

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.