RSFQ Research Articles

Is there a relationship between curvature and inductance in the Josephson junction?

Abstract A Josephson junction is a device made of two superconducting electrodes separated by a very thin layer of isolator or normal metal. This relatively simple device has found a variety of technical applications in the form of Superconducting Quantum Interference Devices (SQUIDs) and Single Electron Transistors (SETs). One can expect that in the near future the Josephson junction will find applications in digital electronics technology RSFQ (Rapid Single Flux Quantum) and in the more distant future in construction of quantum computers. Here we concentrate on the relation of the curvature of the Josephson junction with its inductance. We apply a simple Capacitively Shunted Junction (CSJ) model in order to find condition which guarantees consistency of this model with prediction based on the Maxwell and London equations with Landau-Ginzburg current of Cooper pairs. This condition can find direct experimental verification.

Flux qubit interaction with rapid single-flux quantum logic circuits: Control and readout

We present the results of an analytical study and numerical simulation of the dynamics of a superconducting three-Josephson-junction (3JJ) flux qubit magnetically coupled with rapid single-flux quantum (RSFQ) logic circuit, which demonstrate the fundamental possibility of implementing the simplest logic operations at picosecond times, as well as rapid non-destructive readout. It is shown that when solving optimization problems, the qubit dynamics can be conveniently interpreted as a precession of the magnetic moment vector around the direction of the magnetic field. In this case, the role of magnetic field components is played by combinations of the Hamiltonian matrix elements, and the role of the magnetic moment is played by the Bloch vector. Features of the 3JJ qubit model are discussed during the analysis of how the qubit is affected by exposure to a short control pulse, as are the similarities between the Bloch and Landau-Lifshitz-Gilbert equations. An analysis of solutions to the Bloch equations made it possible to develop recommendations for the use of readout RSFQ circuits in implementing an optimal interface between the classical and quantum parts of the computer system, as well as to justify the use of single-quantum logic in order to control superconducting quantum circuits on a chip.

Investigation Into the Individual Configuration of Superconducting Phase Shift Elements Made of Ferromagnetic Patterns for Reconfigurable Circuits

Reconfigurable superconducting phase shift elements (PSEs) provide high design flexibility in rapid single flux quantum (RSFQ) circuits. Small ferromagnetic patterns were placed on superconducting loops in an RSFQ circuit. The patterns serve as reconfigurable PSEs providing the direction and magnitude of magnetization can be controlled for each pattern individually. A two-dimensional wire mesh architecture was employed to allow for individual configuration and to reduce the number of wires required. Although opposing magnetic fields may occasionally be generated during half-selection using this architecture, experimentally obtained magnetization curves revealed that the orientation of the magnetic field was maintained. An RSFQ circuit, using a reconfigurable PSE, has been successfully demonstrated, potentially leading to large-scale reconfigurable RSFQ circuits

High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic

We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.

32 × 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors

A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlO x /Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm 2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109 multiplications per second.

Frequency Limitation Due to Switching Transition of the Bias Current in Bidirectional RSFQ Logic

Switching time limitations of the ac bias current of Josephson junctions in bidirectional rapid single flux quantum (RSFQ) logic circuits are investigated in order to determine the limits to the maximum possible operating frequency. We introduce a new approach based on modifying the bias current parameters and determining the inductance values in the circuit for reducing the switching transition time of the bias current through the junctions. We have simulated and optimized the timing and the operation of the bidirectional nondestructive readout and Josephson transmission line cells in this respect to demonstrate the results of utilizing the proposed approach. We successfully reduced the unwanted spike-type signals across the inductances which are made through the transitions during the fast switching times limiting the operation frequency. This is while we have also removed the consequent destructive spikes at the output. We have included the effects of other determining parameters of the circuit in this investigation and found their relatively optimal values to improve the temporal behavior of the bidirectional RSFQ cells. The results of the proposed approach leading to the fastest possible operation of the considered gates obtained in this work are thoroughly reported.

Design and Demonstration of Interface Circuits Between Rapid Single-Flux-Quantum and Adiabatic Quantum-Flux-Parametron Circuits

We investigated interface circuits between rapid single-flux-quantum (RSFQ) circuits and adiabatic quantum-flux-parametron (AQFP) circuits for a high-speed and low-power hybrid computing system. In addition, the interface circuits allow us to use long-distance interconnections based on single-flux-quantum (SFQ) passive transmission lines between AQFP gates. The target frequency of interface circuits is several gigahertz. There are two types of interface circuits. The RSFQ/AQFP interface circuit, which transmits a signal from RSFQ circuits to AQFP gates, was realized by coupling an RSFQ toggle flip-flop (TFF) to an AQFP buffer gate. The simulated bias margins of the RSFQ TFF and the excitation current margin of the RSFQ/AQFP interface were 2.22 mA ± 24.7% and 1.71 mA ± 25.0%, respectively. The AQFP/RSFQ interface circuit, which transmits a signal from AQFP gates to RSFQ circuits, was designed by using a high-sensitive magnetically coupled dc/SFQ converter (MC-dc/SFQ) to detect an output current of an AQFP buffer gate. The simulated bias margins of the MC-dc/SFQ and the excitation current margin of the AQFP/RSFQ interface were 0.558 mA ± 20.5% and 1.95 mA ± 36.1%, respectively. We also fabricated and measured the interface circuits.

Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4

We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm 2 advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.

High-Density Shift-Register-Based Rapid Single-Flux-Quantum Memory System for Bit-Serial Microprocessors

We demonstrated a high-density shift-register-based random access memory system based on rapid single-flux-quantum (RSFQ) logic. This memory system was developed to be integrated with bit-serial RSFQ microprocessors, which are called the CORE e series. It is composed of a shift-register array to store data, a decoder to select the shift register pointed to by a given address, and mergers to output data. To achieve high density, we introduced a new memory system structure and designed compact storage elements and other peripheral components. We integrated two 256-bit memory systems (32 entries for 8-bit data and instructions each) with a CORE e microprocessor and fabricated it using the National Institute of Advanced Industrial Science and Technology 10-kA/cm2 Advanced Process. The area occupied by each memory system is 2.69 mm2. We obtained correct operations for all of the addresses in low-frequency tests. The typical measured bias margin was 86%–106%.

Investigation of Readout Cell Configuration and Parameters on Functionality and Stability of Bi-Directional RSFQ TFF

Considering the two main categories of rapid single flux quantum gates with destructive and nondestructive readout process, we have investigated the effects of readout cell topology and involved critical parameters on the proper functionality and stability of the states of the newly developed bidirectional T flip-flops (TFFs). It is observed that instabilities and fluctuations in the state of the gate (memory of TFF) after each transition determine the minimum time intervals between the clock pulses set by the ac bias current, further limiting the ultimate operation frequency of the circuits. The absolute values of the current levels of the junctions at each state, which play an important role in the behavior of the cell, are studied, and their variations over several consequent pulses are stabilized by optimizing the cell parameters. The appropriate values of the circuit and junction parameters are found, resulting in the optimum operation of the circuit for having the best margins possible. We report on the investigated circuit topology and parameter optimizations of the readout circuit of the considered bidirectional TFF.

Low-Power Digital Gates in ERSFQ and nSQUID Technology

We designed and tested low-power digital gates based on the energy-efficient rapid single flux quantum (ERSFQ) and on the reversible nSQUID logic. The ERSFQ circuit consists of a series of 13 toggle flip-flops (TFFs), where the bias resistors are replaced by inductors which generate no energy dissipation in the static mode, resulting in a power consumption orders of magnitude below that of traditional RSFQ circuits during operation. The ERSFQ circuits were fabricated with HYPRES' standard 4.5-kA/cm2 process and tested up to 20 GHz. The RF input level was about −25 dBm 50 $\Omega$ matched, and the output level was 400 $\mu\text{Vpp}$ . The nSQUID ring with “NOT” gates was fabricated with HYPRES' standard 1-kA/cm2 process. The “0” and “1” input logic signals were realized injecting ±5 mA of current in a superconductive coil, obtaining 6 $\mu\text{Vpp}$ of amplitude as output signal. The test was performed at low frequency in order to verify the functionality and the ultralow power consumption.

Rapid Single-Flux-Quantum Circuits Fabricated Using <inline-formula> <tex-math notation="TeX">$\hbox{20}\hbox{-}\hbox{kA}/\hbox{cm}^{2}$</tex-math></inline-formula> <inline-formula> <tex-math notation="TeX">$\hbox{Nb}/\hbox{AlO}_{x}/\hbox{Nb}$</tex-math></inline-formula> Process

We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm 2 process based on conventional Nb/AlO x /Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.

Improved <inline-formula> <tex-math notation="TeX">$\hbox{All-MgB}_{2}$</tex-math></inline-formula> Toggle Flip-Flop Circuit With Increased Operating Speed and Temperature Range

We have fabricated and tested rapid single flux quantum toggle flip-flop circuits using self-shunted MgB 2 / MgO/MgB 2 Josephson junctions with a single ground layer. The MgB 2 films were deposited using HPCVD, and the MgO barrier was deposited using DC reactive sputtering. We highlight the circuit's voltage divider operation dependence on current bias and temperature which show operation from 7 to 30 K. The highest attained operating speed is 335 GHz at 7 K. These results demonstrate the versatile temperature range and speed of MgB 2 digital circuits.

Power-Optimized Temperature-Distributed Digital Data Link

Interfacing superconducting rapid single flux quantum logic with room temperature electronics requires the development of low-power semiconductor circuitry capable of operating at tens of Gb/s while maintaining sufficient signal to noise to achieve acceptable bit-error-rates. Such data-links must operate with sufficiently low power consumption to permit tens to hundreds of parallel channels to coexist in a single cryostat. This requires a careful trade-off between the power and noise performance of the cryogenically cooled digital amplifiers. Previously demonstrated ultra low-power cryogenic-to-room temperature digital data links have been limited to data rates on the order of a few Gb/s. In this paper we demonstrate a temperature distributed amplifier chain optimized for 30 Gb/s data transmission and consuming just 140 microwatts at 4 K.

Study of $\hbox{MgB}_{2}$ Josephson Junction Arrays and Sub- $\mu\hbox{m}$ Junctions

Sandwich-type MgB 2 /MgO/MgB 2 Josephson junctions with sizes ranging from 0.5 μm × 0.5 μm to 10 μm × 10 μm were fabricated using electron beam lithography. The junctions show critical current densities as high as 130 kA/cm 2 . The smallest of the junctions operated free of hysteresis below 4.2 K. They may be ideal for use in rapid single flux quantum circuits with no requirement for external shunt resistors. The 10-μm junctions show good agreement with the expected Fraunhofer-like modulation of critical current with magnetic field; however, the smaller junctions show a sinusoidal modulation, indicating an anomalous current distribution that needs to be further investigated. Series arrays of Josephson junctions were made to quantitatively study the uniformity of junction parameters, which shows a 54% spread in critical current of a 100 junction array of 4-μm junctions.

ERSFQ 8-Bit Parallel Adders as a Process Benchmark

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

Wave-Pipelined eSFQ Circuits

We have designed and tested energy-efficient single flux quantum (eSFQ) circuits suitable for wave-pipelined architectures. The high energy-efficiency of eSFQ circuits combined with the sequential nature of SFQ logic makes eSFQ especially suitable for energy-efficient variants of highly-pipelined circuits such as modern arithmetic logic units (ALUs), without penalty to the clock speeds available to RSFQ logic. In previous work, we have demonstrated working eSFQ circuits in the form of shift registers, deserializers, counters. Here we expand on this work by introducing a means of moving data through eSFQ circuits without the need for buffering at every step, resembling the wave-pipelined architecture characterizing many large modern logic circuits. Specifically, we present a pipeline-friendly JTL, confluence buffer, and half adder, comprising the core components of many adder architectures. We also show how such an eSFQ full adder naturally lends itself to utilization in a computation pipeline. We report experimental demonstration of circuits manufactured in Hypres's 4.5 kA/cm 2 process.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33mA for the PRNG, and 1677 junctions and 218mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Observation of 0–π transition in SIsFS Josephson junctions

The 0–π transition in Superconductor-Insulator-superconductor-Ferromagnet-Superconductor (SIsFS) Josephson junctions (JJs) was investigated experimentally. As predicted by theory, an s-layer inserted into a ferromagnetic SIFS junction can enhance the critical current density up to the value of an SIS tunnel junction. We fabricated Nb′ | AlOx | Nb | Ni60Cu40 | Nb JJs with wedge-like s (Nb) and F (Ni60Cu40) layers and studied the Josephson effect as a function of the s- and F-layer thickness, ds and dF, respectively. For ds = 11 nm, π-JJs with SIFS-type jc(dF) and critical current densities up to jcπ=60 A/cm2 were obtained at 4.2 K. Thicker ds led to a drastic increase of the critical current decay length, accompanied by the unexpected disappearance of the 0–π transition dip in the jc(dF) dependence. Our results are relevant for superconducting memories, rapid single flux quantum logic circuits, and solid state qubits.

Symmetrical Josephson vortex interferometer as an advanced ballistic single-shot detector

We consider a ballistic detector formed in an interferometer manner which operational principle relies on Josephson vortex scattering at a measurement potential. We propose an approach to symmetrize the detector scheme and explore arising advantages in the signal-to-noise ratio and in the back-action on a measured object by means of recently presented numerical and analytical methods for modeling of a soliton scattering dynamics in the presence of thermal fluctuations. The obtained characteristics for experimentally relevant parameters reveal practical applicability of the considered schemes including possibility of coupling with standard digital rapid single flux quantum circuits.