Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits

Abstract

A technology mapping method for reducing the logic stages of RSFQ logic circuits is proposed. Technology mapping, which generates netlists for a target technology from a device-independent form, is the final step in logic synthesis. This method introduces clockless logic gates working without clock pulses into the resultant netlists during technology mapping to reduce the number of logic stages. The reduction of logic stages leads to a reduction of latency in clock cycles and circuit size of clock distribution. The introduction of clockless gates is accomplished using a special supergate library used in technology mapping. The design method of a special library containing supergates, including clockless gates, is shown. A modification to reduce the delay caused by clockless gates is also presented. The proposed method is implemented and evaluated using academic design tool ABC. The evaluation results show a reduction of over 30% in the logic stages and a reduction of over 20% in the number of clocked gates, including D flip-flops for path balancing.