Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates

Abstract

This article proposes a method for generating RSFQ logic circuits utilizing special RSFQ gates in logic synthesis. It is suited for the standard technology mapping flow used in logic synthesis tools and enables generating RSFQ circuits utilizing confluence buffers (CBs) and resettable DFFs (RDFFs), to reduce the number of clocked gates by reduction of logic depth. A library of supergates, each consisting of several gates, is used to compose a resultant circuit in the technology mapping. In this article, a library containing supergates including those special gates is generated and is utilized to design circuits with the gates. First, a generation of a supergate library is proposed to introduce CBs and RDFFs, which realize logic OR without clock pulses and a fused function of logic AND and NOT, respectively. The generated library contains supergates including the special gates and they are used to compose the resultant circuits with the special gates. A mapping approach is also proposed. It distinguishes non-clocked gates such as CBs and clocked gates. It takes the number of inserted DFFs for path balancing into account to reduce the number of clocked gates. The method was implemented into the state-of-the-art academic EDA tool, i.e., ABC, and was evaluated. Evaluation results show that the number of clocked gates is reduced by about 30% from the original ABC with path-balancing DFFs.