Preface of the “Symposium on Logic Synthesis for Programmable Logic Devices”

Abstract

Logic synthesis is an indirect link between design description and technology mapping. In the result of synthesis process an implementation in terms of an interconnection of logic gates, flip-flops, LUTs, etc. is generated. Typically, synthesis is performed for an objective function, such as minimizing the number of logic blocks (area), delay of interconnection, minimizing the power consumed, or making the implementation more testable. Logic synthesis is typically separated into two stages: technology-independent optimization, followed by a technology mapping. Technology mapping is the process of expressing a boolean network in terms of elements characteristic for a given technology (or device family). The aim of the symposium is to show all aspects of logic synthesis dedicated for Programmable Logic Devices.