Rapid Single Flux Quantum Circuits Research Articles

Quantum thermodynamics with a single superconducting vortex.

We demonstrate complete control over dynamics of a single superconducting vortex in a nanostructure, which we coin the Single Vortex Box. Our device allows us to trap the vortex in a field-cooled aluminum nanosquare and expel it on demand with a nanosecond pulse of electrical current. Using the time-resolving nanothermometry we measure [Formula: see text] joules as the amount of the dissipated heat in the elementary process of the single-vortex expulsion. Our experiment enlightens the thermodynamics of the absorption process in the superconducting nanowire single-photon detectors, in which vortices are perceived to be essential for a formation of a detectable hotspot. The demonstrated opportunity to manipulate a single superconducting vortex reliably in a confined geometry comprises a proof of concept of a nanoscale nonvolatile memory cell with subnanosecond write and read operations, which offers compatibility with quantum processors based either on superconducting qubits or on rapid single-flux quantum circuits.

Simulations of superconducting quantum gates by digital flux tuner for qubits

Abstract The interconnection bottleneck caused by limitations of cable number, inner space and cooling power of dilution refrigerators has been an outstanding challenge for building scalable superconducting quantum computers with the increasing number of qubits in quantum processors. To surmount such an obstacle, it is desirable to integrate qubits with quantum–classical interface (QCI) circuits based on rapid single flux quantum (RSFQ) circuits. In this work, a digital flux tuner for qubits (DFTQ) is proposed for manipulating flux of qubits as a crucial part of the interface circuit. A schematic diagram of the DFTQ is presented, consisting of a coarse tuning unit and a fine-tuning unit for providing magnetic flux with different precision to qubits. The method of using DFTQ to provide flux for gate operations is discussed from the optimization of circuit design and input signal. To verify the effectiveness of the method, simulations of a single DFTQ and quantum gates including a Z gate and an iSWAP gate with DFTQs are performed for flux-tunable transmons. The quantum process tomography corresponding to the two gates is also carried out to analyze the sources of gate error. The results of tomography show that the gate fidelities independent of the initial states of the Z gate and the iSWAP gate are 99.935% and 99.676%, respectively. With DFTQs inside, the QCI would be a powerful tool for building large-scale quantum computers.

Research on the current compensation mechanism of FJTL in ERSFQ

Energy-efficient rapid single flux quantum (ERSFQ) devices have unique energy advantages with a power consumption of less than 0.001fJ per single-bit switch, even considering the energy required for the refrigeration system, achieving ultra-low energy consumption of sub-fJ/bit. Combined with its typical operating frequency in the tens of GHz range, ERSFQ circuits have the potential to realize computing chips with extremely high computational power and energy efficiency, making them highly promising for applications in the post-Moore era. However, the performance improvement of ERSFQ circuits faces two challenges. One is how to reduce the size of their feeding Josephson transmission line (FJTL), which is required to stabilize the voltage bias of the ERSFQ circuits. The second challenge is how to improve their bias margin. The measured bias margin of ERSFQ circuits is relatively smaller than for Rapid Single Flux Quantum (RSFQ) circuits. This study investigates the current compensation mechanism of the FJTL and derives a formula for the compensating current ΔI in the main logic circuit by each pulse input to the FJTL. Based on the formula, a method is proposed to enhance the bias margin of ERSFQ circuits while reducing the size of FJTL by applying feeding pulses into the FJTL. We applied this method to an 8-bit ERSFQ shift register (SR), where the size of its FJTL is 4 JTLs (each JTL consists of 2 Josephson junctions). The measurement demonstrated an improvement of the bias margin from [84 %, 104 %] to [38 %, 104 %], confirming the feasibility of the proposed method. Furthermore, by comparing the measurement results of an 8-bit ERSFQ SR, where the size of its FJTL is 6 JTLs, it is demonstrated that applying this method can also reduce the size of the FJTL while maintaining a large margin.

Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.

Timing Regulation Scheme for RSFQ Circuit

Rapid single-flux-quantum (RSFQ) circuit requires an accurate timing scheme to maintain correct function, especially under a very high clock frequency. However, the reported timing regulation schemes have issues, including the bias margin of the circuit being small and the bias margin decrement caused by imprecise timing constraints. This paper proposes a new timing regulation scheme based on clock-follow-data clocking that can solve the problems. The scheme uses the unique structure of the RSFQ circuit to eliminate the impact caused by different timing libraries and extend the biasing margin. The simulation results of the XOR gate under various timing regulation schemes demonstrated that the proposed scheme could obtain the maximum STA bias margin. Also, the STA bias margin of the 4-bit parallel arithmetic logic unit (ALU) designed using the timing regulation scheme proposed in this paper was increased by 5%, the PSCAN2 bias margin was increased by 7.4%, and 36 ps reduced latency. The ALU fabricated using the “SIMIT Nb03” process was successfully measured with correct operation at low frequency. It showed this scheme could provide accurate timing constraints range and enhances circuit bias margin.

Demonstration and Comparison of On-Chip High-Frequency Test Methods for RSFQ Circuits

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

Striking a Good Balance Between Area and Throughput of RSFQ Circuits Containing Feedback Loops

Electronic design automation solutions are being developed to support the synthesis and physical design optimization of Rapid Single Flux Quantum (RSFQ) logic circuits with hundreds of thousands of logic cells. The clocked feature of synchronous RSFQ cells results in gate-level pipelined designs, requiring a large number of path-balancing D-flipflops (DFFs). In addition, one also faces the challenge of maintaining high throughput for RSFQ circuits containing feedback loops. To enforce the coincidence of the input and feedback patterns, one can apply a new input pattern every <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L$</tex-math></inline-formula> cycles, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L$</tex-math></inline-formula> is the length of the feedback loop. Consequently, the throughput of circuits with feedback loops is only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1/L$</tex-math></inline-formula> of the clock frequency. In this paper, we present two methods to improve the performance and area of RSFQ circuits, especially targeting circuits with feedback loops: (i) An area-oriented optimization method that removes the path-balancing DFFs by capturing and repeating input patterns. (ii) A throughput-oriented optimization method that enables an RSFQ circuit to receive and correctly process an input pattern every clock cycle. For a large circuit such as S526 in the ISCAS89 benchmark circuits, the circuit can initially receive an input pattern only every 9 cycles. As a result of applying our area-oriented optimization, the circuit admits 33% fewer logic cells while receiving input patterns every 11 cycles. Alternatively, our throughput-oriented optimization yields a circuit that can receive new input patterns on every cycle with nearly the same cell count.

Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits

This paper proposes a fast automatic gate placement method for gate-level-pipelined Rapid Single Flux Quantum (RSFQ) circuits that are designed to have a high throughput. In such circuits, the gates in a pipeline stage are placed in a column and wires are routed in the area between adjacent columns. In wire routing, wire length-matching is performed. The proposed method performs gate placement for a given netlist to minimize the sum of the maximum distance between connected gates in each pair of adjacent columns. It leads to short wire extensions in wire length matching for increasing the operation frequency and small circuit area. The proposed method consists of a recursive procedure including two placements, selecting a pivot column, and determining the gate placement in the pivot column. The netlist is divided into two netlists with the pivot column. The recursive procedure performs gate placements for the two divided netlist. It is repeated until the location of every gate is determined. We implemented a placement tool by the proposed method and performed the gate placement for three circuits including several hundreds of gates. The proposed placement was 14 to 40 times faster than a placement based on simulated annealing where the sum of the maximum distance between connected gates is approximately the same.

60-GHz Single Flux Quantum Pulse Transfer Circuit for Serial Biasing

Serial Biasing (SB) is a technique to reduce the total DC bias current of Rapid Single Flux Quantum (RSFQ) circuits by partitioning a design into several islands with isolated grounds and sequential biasing. In this paper we focus on the design of a driver-receiver pair (DRP) to transfer pulses between islands that are galvanically isolated for pulse streams. We discuss both DRP itself and the structure for its testing, that comprises several DRPs connected in series, on-chip pseudo random binary sequence (PRBS) generator for circuit stimulation, and HF output interface. We use the layout of DRPs’ chain as an example to illustrate the advantage of the grapevine (GV) approach, introduced earlier, to manage the bias current flowing into and out of an island. The GV current management technique is analyzed by both electromagnetic simulations and measurement, compared, and contrasted with the so-called ‘straightforward’ (SF) approach. The maximum operational frequency for SF test structure was 10 GHz with zero margins for the SB current. Measurements of the GV structure at 10 GHz demonstrated BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> with ±5.8% margins for SB current. We observed the correct operation of the 5-island DRP chain up to 60 GHz using the grapevine approach for SB current management. All chips were fabricated at MIT Lincoln Laboratory using SFQ5ee fab node.

Demonstration of Interface Circuits for Adiabatic Quantum-Flux-Parametron Cell Library Using an Eight-Metal Layer Superconductor Process

In this paper, we designed and demonstrated interface circuits between AQFP (adiabatic quantum-flux-parametron) and RSFQ (rapid single-flux-quantum) circuits according to the established AQFP and RSFQ cell libraries using the MIT LL SFQ5ee process. The principles of these interfaces are based on ones that were previously designed and demonstrated using a four-metal-layer superconductor process. The AQFP-to-RSFQ interface is based on an RSFQ comparator, where an output current from an AQFP buffer is converted to an SFQ pulse output. The RSFQ-to-AQFP interface is based on an RSFQ D flip-flop, where the internal state of the D flip-flop is read out by an AQFP buffer. Thanks to the eight-metal-layer process, the interfaces can be designed with reduced circuit area compared to original designs with the four-metal-layer process. We designed, fabricated, and tested an AQFP-RSFQ hybrid multiplexer test circuit as an example of utilization of the interfaces, which results in correct operation with reasonably wide bias margins in low-frequency tests.

High density fabrication process for single flux quantum circuits

We implemented, optimized, and fully tested a superconducting Josephson junction fabrication process over multiple runs tailored for integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient rapid single flux quantum (ERSFQ) circuits with critical currents reduced by a factor of ∼10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 μA unit critical current fabricated with 10 μA/μm2 critical current density. In order to circumvent the substantial size increase in the SFQ circuit inductors, we employed an NbN high kinetic inductance layer with 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with 4.0 Ω/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 μm height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive process control monitor chip set.

VHDL models of the basic dual-rail asynchronous RSFQ gates

This paper presents a basic approach for applying Very High-Speed Integrated Circuits Hardware Description Language (VHDL) descriptions of dual-rail rapid single flux quantum circuits (RSFQ). Because RSFQ is naturally pulsed, dual-rail data encoding encourages event driven data processing at very high speeds. A method for suitable simulation models of the basic asynchronous RSFQ gates is described. The realization of VHDL models is performed in relation with the subsequent implementation for simulation and parameter optimization of complex logic cells.

Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . We discuss future steps to improve the SB technique.

On-chip test vector generation and downsampling for testing RSFQ circuits

An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits

It is known that rapid single-flux-quantum (RSFQ) circuit technology and its energy-efficient derivatives are considered promising technology in superconducting digital applications. Given an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> -stage logical netlist with a set of logic gates and D-type flip-flops (DFFs) in an RSFQ circuit, based on the construction of three different gate components inside one gate column, the RSFQ circuit can be treated as a pipelined architecture with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> gate components inside <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> gate columns. To minimize the routing area in the pipelined architecture of an RSFQ circuit, an efficient algorithm can be proposed to minimize the total vertical wirelength in a fixed-order placement. First, based on the construction of the initial fixed-order placement and the reduction of the total vertical minimum length using one upward-shifting operation, a propagation-based fixed-order placement (PFP) can be obtained by using an on-column placement process. Based on the determination of the available gate clusters inside the gate columns, an iterative matching-based shifting process can be further used to reduce the total vertical wirelength in a fixed-order placement. Finally, based on the determination of the available gate blocks in a modified fixed-order placement, an iterative shifting process can be used to reduce the total vertical wirelength in the modified fixed-order placement. Compared with the modified simulated-annealing (SA)-based algorithm with three initial temperatures, 100, 1000, and 100000, the experimental results show that our proposed algorithm can use 3.4%, 2.7%, and 2.1% of CPU time to reduce 3.5%, 0.5%, and 0.3% of the total vertical wirelength in a final fixed-order placement for five tested RSFQ circuits on the average, respectively. Clearly, the proposed algorithm is efficient in the construction of a fixed-order placement in an RSFQ circuit.

QuCTS—Single-Flux Quantum Clock Tree Synthesis

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.

Extended FDTD Method for Coanalysis of Superconducting Passive Transmission Lines and Josephson Junction Drivers and Receivers

In rapid single-flux quantum circuits, the signal integrity problem of superconducting passive transmission lines (PTLs) becomes critical. In this article, an extended 3-D finite-difference time-domain (FDTD) method is proposed for coanalysis of superconducting PTLs and Josephson junction (JJ) drivers and receivers. The central difference FDTD scheme is used for PTLs, and the backward difference method is adopted for JJs, which are introduced to FDTD cells as lumped elements. Due to the nonlinearity of JJs, the Newton–Raphson method is introduced to solve the boundary condition of the FDTD method. Compared with the 1-D FDTD method of the transmission line model of PTLs, the proposed method performs full-wave analysis of the physical structure of PTLs. Therefore, the proposed 3-D FDTD method is theoretically more accurate than the conventional method by avoiding parameter extraction and circuit analysis.

Compact Stochastic Computing Circuits Using the Latching Function of RSFQ Circuits for Computing Polynomials

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

A new LFSR based high-frequency test method for RSFQ circuit

Rapid single flux quantum (RSFQ) circuits have the advantages of high speed and low power consumption. The typical frequency of the RSFQ circuits is tens of GHz. Therefore, it is necessary to reliably test the high-frequency performance of RSFQ circuits simply and effectively. This paper proposes a new on-chip high-frequency testing method, which uses pseudo-random sequences generated by linear feedback shift register (LFSR) as the test vectors, and the output shift registers (SRs) to store the last piece of high-frequency testing result and read out it at low-frequency. Unlike the traditional high-frequency demonstration method of using the Input/Output SRs, our testing system can automatically generate a large number of test vectors to test the circuit at high frequency at low cost, making the whole high-frequency demonstration more reliable and convincing. On the other hand, this method is also a feasible and straightforward on-chip high-frequency test method for various RSFQ circuits. This work verified the proposed method, and the highest test frequency can reach 54 GHz while the circuit shows good operating margins.

Pulse Interfaces and Current Management Techniques for Serially Biased RSFQ Circuits

As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the current by placing identical digital blocks on islands with isolated grounds and bias them sequentially. There are typically two implementations that are essential for the SB approach: the design of a driver-receiver pair (DRP) for inter-island pulse transport and the current management technique to handle the bias current flowing into and out of an island. While a DRP with good fidelity is essential for any serially biased circuit, the current management becomes critical for designs with relatively large bias current. In this paper, we address the latter. First, we propose a grapevine biasing scheme for serial bias current management. Second, we implement the technique using two exemplar circuits: the parallel counter and the digital decimation filter. We report the low and high speed test results up to 50 GHz for both circuits fabricated at MIT-LL in the SFQ5ee 10 kA&#x002F;2 &#x2126; fab node.