Rapid Single Flux Quantum Cell Research Articles

Demonstration of Interface Circuits for Adiabatic Quantum-Flux-Parametron Cell Library Using an Eight-Metal Layer Superconductor Process

In this paper, we designed and demonstrated interface circuits between AQFP (adiabatic quantum-flux-parametron) and RSFQ (rapid single-flux-quantum) circuits according to the established AQFP and RSFQ cell libraries using the MIT LL SFQ5ee process. The principles of these interfaces are based on ones that were previously designed and demonstrated using a four-metal-layer superconductor process. The AQFP-to-RSFQ interface is based on an RSFQ comparator, where an output current from an AQFP buffer is converted to an SFQ pulse output. The RSFQ-to-AQFP interface is based on an RSFQ D flip-flop, where the internal state of the D flip-flop is read out by an AQFP buffer. Thanks to the eight-metal-layer process, the interfaces can be designed with reduced circuit area compared to original designs with the four-metal-layer process. We designed, fabricated, and tested an AQFP-RSFQ hybrid multiplexer test circuit as an example of utilization of the interfaces, which results in correct operation with reasonably wide bias margins in low-frequency tests.

Impedance Matching of Passive Transmission Line Receivers to Improve Reflections Between RSFQ Logic Cells

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

Relaxation method in description of RAM memory cell in RSFQ computer

PurposeThe lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM.Design/methodology/approachA new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored.FindingsTwo basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions.Research limitations/implicationsThe proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5).Practical implicationsCurrently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power.Social implicationsComputation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time.Originality/valueThe publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.

Automated State Machine and Timing Characteristic Extraction for RSFQ Circuits

We present a heuristic for the automated extraction of state machine representations of rapid single-flux-quantum (RSFQ) digital logic circuits given a circuit SPICE representation. Furthermore, this heuristic uses the SPICE netlist to extract timing characteristics for the creation of a hardware description language (HDL) implementation of the circuit. This facilitates RSFQ logic design at an HDL level rather than a Josephson junction level. The state machine extraction method can be also used for the automatic creation of test benches for circuit yield analysis, as well as optimization algorithms. An example of the automatic extraction of the state machine representation, timing characterization, and HDL implementation is demonstrated for a complex RSFQ cell.

Development of an Optimization Tool for RSFQ Digital Cell Library Using Particle Swarm

Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.

SFQ Circuits With Ground Plane Hole-Assisted Inductive Coupling Designed With InductEx

The design of single flux-quantum (SFQ) circuits requires well-defined inductances. In many cases these are created by irregular geometries and a computer-aided design tool is necessary for inductance calculations. This becomes a challenging task in cases where no ground plane is used and thus three-dimensional calculations are required. For this purpose, InductEx was developed and verified successfully for simple structures. In this work we take the next step and demonstrate the applicability of InductEx to the design of rapid single flux-quantum (RSFQ) cells. We use InductEx for inductance modeling as an integral part of the design cycle for an RSFQ cell with flux quantum transfer via mutual inductance and for a DC-reprogrammable logic circuit with similar inductive coupling. The relation between coupling factor and self-inductance is optimized in the circuit layout. All coupling structures are duplicated in SQUID modulation test circuits to measure and verify calculation accuracy. We find excellent agreement between the calculated and measured inductance values. Furthermore, the operational area of the basic cell is determined and compared with similar investigations reported earlier. Based on this comparison we conclude that InductEx is a valuable inductance design tool, and that mutual coupling in structures using ground plane holes and RSFQ-compatible self-inductances can be modeled and designed reliably.

Design and Operation of RSFQ Cell Library Fabricated by Using a 10-${\rm kA/cm}^{2}$ Nb Technology

A 10-kA/cm2 Nb/AlOchi/Nb junction technology for rapid single flux quantum (RSFQ) integrated circuits has been developed. Modifying our standard 1.6-kA/cm2 cell library, we have implemented elementary cells used to build RSFQ digital-to-analog converters for ac voltage standard applications. The 10-kA/cm2 library cells have been fabricated by utilizing existing process tools. Correct operations of the circuits have been confirmed at low speed. The maximum operating frequencies evaluated by an average-voltage measurement technique were consistent with the scaling rules of RSFQ circuits.

Tuning of the RSFQ Gate Speed by Different Stewart-McCumber Parameters of the Josephson Junctions

At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.

Design and fabrication of RSFQ cell library for middle-scale applications

We present the development of a rapid single flux quantum (RSFQ) standard cell library for middle-scale applications. The library includes elementary cells frequently used to build large circuit blocks. The standard cells were designed for a simple process with 8 mask levels. The circuits were optimized and laid out to minimize effects of high parasitic inductance associated with a single ground plane layer. Circuit parameters on the wafer were determined by electrical measurements on parametric test circuits, which gave feedback on the design and process. All cells were individually fabricated and tested, and the design and layout were confirmed.

Rapid single-flux quantum logic using π-shifters

We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.

Cell-based design methodology for BDD RSFQ logic circuits: tolerance of basic cells to circuit parameter variations

We have proposed a cell-based design approach based on a binary decision diagram (BDD) for the design of rapid single flux quantum (RSFQ) logic circuits. In this design approach, any logic function can be implemented by simply embedding the limited number of basic cells. We have constructed a BDD RSFQ cell library and prepared a top-down CAD environment. In this study, we investigated the tolerance of the BDD RSFQ basic cells to the circuit parameter variations. It was found that theoretical and measured dc bias margins of the basic cells agree well if we assume appropriate parameter variations due to the fabrication process. The dependence of the dc bias margin of the circuits on the circuit size was also examined, where we have implemented a 2-bit multiplexer, a 4-bit data-driven self-timed shift register and a 1-bit ALU. The low-speed test results reveal that dc bias margin of the circuits containing several hundreds of Josephson junctions is about ±15%, whereas theoretical dc bias margin is about ±33%.This paper was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19–22 June 2001.

Cell-based top-down design methodology for RSFQ digital circuits

We propose a cell-based top-down design methodology for rapid single flux quantum (RSFQ) digital circuits. Our design methodology employs a binary decision diagram (BDD), which is currently used for the design of CMOS pass-transistor logic circuits. The main features of the BDD RSFQ circuits are the limited primitive number, dual rail nature, non-clocking architecture, and small gate count. We have made a standard BDD RSFQ cell library and prepared a top-down design CAD environment, by which we can perform logic synthesis, logic simulation, circuit simulation and layout view extraction. In order to clarify problems expected in large-scale RSFQ circuits design, we have designed a small RSFQ microprocessor based on simple architecture using our top-down design methodology. We have estimated its system performance and compared it with that of the CMOS microprocessor with the same architecture. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large chip area.

Development of highly integrated RSFQ circuits on the basis of intrinsically shunted Josephson junctions

At PTB, for application in rapid single flux quantum (RSFQ) and voltage standard circuits, the development of highly integrated SDE circuits is focused on devices based on intrinsically shunted Josephson junctions in the SINIS and SNS technologies. In SINIS technology, the fabrication process has been optimized to values of the critical current density of j C=500 A/cm 2 and the characteristic voltage of V C=190 μV. To raise the circuit integration level, successive steps of development are shown by the example of the layout of an elementary RSFQ cell designed for higher values of j C. In SNS technology, a fabrication process has been developed to produce small ramp-type junctions with contact areas smaller than 0.4 μm 2 and with values for j C and V C of about j C=200 kA/cm 2 and V C=20 μV. The design allows the SNS junction size to be further reduced down to the deep sub-micron range.

Novel design of rapid single flux quantum logic based on a single layer of a high-T c superconductor

We suggest a new design of rapid single flux quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. Small inductances of about 10 pH, obligatory for RSFQ circuits, are formed as narrow slits of widths comparable to the London penetration depth (≂0.15 μm). The design allows us to decrease the geometric size of the RSFQ cell. Test circuits with YBaCuO grain boundary junctions on asymmetric 32° Y– ZrO2 bicrystals were used to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 μm slit was found to be 0.7–0.8 pH/μm.

A new design approach for High-T/sub c/ based RSFQ logic

We suggest a new design of Rapid Single Flux Quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. The small inductances of about 10 pH, that are obligatory for the RSFQ applications, are formed as narrow slits with width comparable to the London penetration depth (/spl cong/0.15 /spl mu/m). The design allows us to decrease the geometric size of the RSFQ cell and can be applied to low-T/sub c/ circuits as well. Test circuits have been implemented using YBaCuO grain boundary junctions on assymmetric 32/spl deg/Y-ZrO/sub 2/ bi-crystals to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 pm slit was determined to be 0.7pH//spl mu/m. We present a new design and a computer simulation of a flip-flop circuit based on these inductance measurements. To realize these circuits experimentally one needs at least two grain boundaries, separated by a distance of 10 to l5 /spl mu/m, or to use bi-epitaxial or step-edge junction technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>