Randomness Test Suite Research Articles

Cryptographic transistor for true random number generator with low power consumption.

We design a cryptographic transistor (cryptoristor)-based true random number generator (tRNG) with low power consumption and small footprint. This is the first attempt to use irregular and unpredictable operation-induced randomness of a cryptoristor as an entropy source. To extract discrete random numbers with a binary code from the cryptoristor, we developed a noise-coupling analog-to-digital converter. This converter not only converts analog signals to digital random bits but also improves the randomness of the entropy source with low power consumption. The randomness of the cryptoristor is attributed to the random carrier multiplications with the creation and stochastic carrier escape as destruction, which occurs iteratively as long as the input current is fed. The cryptoristor-based tRNG passed 15 randomness test suites of NIST Special Publication 800-22. It is robust to iterative operational stresses and to ambient temperature changes, making it an attractive option for hardware-based security solutions in the Internet of Things due to its low power consumption and small size.

Quantum-Secure Hybrid Blockchain System for DID-Based Verifiable Random Function with NTRU Linkable Ring Signature

In this study, we present a secure smart contract-based Verifiable Random Function (VRF) model, addressing the shortcomings of existing systems. As quantum computing emerges, conventional public key cryptography faces potential vulnerabilities. To enhance our VRF’s robustness, we employ post-quantum Ring-LWE encryption for generating pseudorandom sequences and a NTRU lattice-based linkable ring signature scheme. Given the computational intensity of this approach and associated on-chain gas costs, we propose a hybrid architecture of VRF system where both on-chain and off-chain can communicate in a scalable and secure way. Our decentralized VRF employs multi-party computation (MPC) with blockchain-based decentralized identifiers (DID), ensuring the collective efforts of enhanced randomness and security. We show the security and privacy advantages of our proposed VRF model with the approximated estimation of overall temporal and spatial complexities. We also evaluate our VRF MPC model’s entropy and outline its Solidity smart contract integration. This research also provides a method to produce and verify the VRF output’s proof, optimal for scenarios necessitating randomness and validation. Lastly, using NIST SP800-22 test suite for randomness, we demonstrate the commendable result with a 97.73% overall pass rate on 11 standard tests and 0.5459 of average 𝑝-value for the total 176 tests.

WALLAX: A memristor-based Gaussian random number generator

Generating Gaussian random numbers is essential in many applications such as cryptography, games, and computer simulations. Although software Gaussian Random Number Generators (GRNG) are widely used, hardware designs have been explored for their faster speed and lower computational cost. However, hardware GRNGs usually occupy large silicon areas when implemented in Complementary Metal Oxide Semiconductor (CMOS) technology, especially for their essential Uniform Random Number Generator (URNG) part. Here, we present a memristor-based GRNG, named WALLAX, conceived from the Wallace method to generate random numbers iteratively. This GRNG circuit benefits not only from the fully parallel analog-based Vector Matrix Multiplication (VMM) feature of memristive crossbars but also harness the intrinsic stochastic switching behaviour of the memristive devices to efficiently produce truly random numbers. The vector-matrix multiplication of WALLAX is implemented on the memristive crossbar, while its random fetching step is realized by a URNG based on the stochastic switching nature of memristors. WALLAX successfully passes all the tests in the NIST 800-22 randomness test suite with 105 numbers generated and five goodness-of-fit tests with various pool sizes and effectively reduces the power and area consumption by 68.78% and 70.0% compared to digital implementations of the same GRNG method. The impact brought by memristor non-idealities is investigated by simulating the proposed structure with 1000 pools under various scenarios. Wire resistance and the stuck of state, each result in a 2.2% and 12.3% reduction in test pass rate within the tested range, respectively.

Generating Class-Level Integration Tests Using Call Site Information

Search-based approaches have been used in the literature to automate the process of creating unit test cases. However, related work has shown that generated unit-tests with high code coverage could be ineffective, i.e., they may not detect all faults or kill all injected mutants. In this paper, we propose CLING, an integration-level test case generation approach that exploits how a pair of classes, the caller and the callee, interact with each other through method calls. In particular, CLING generates integration-level test cases that maximize the Coupled Branches Criterion (CBC). Coupled branches are pairs of branches containing a branch of the caller and a branch of the callee such that an integration test that exercises the former also exercises the latter. CBC is a novel integration-level coverage criterion, measuring the degree to which a test suite exercises the interactions between a caller and its callee classes. We implemented CLING and evaluated the approach on 140 pairs of classes from five different open-source Java projects. Our results show that (1) CLING generates test suites with high CBC coverage, thanks to the definition of the test suite generation as a many-objectives problem where each couple of branches is an independent objective; (2) such generated suites trigger different class interactions and can kill on average 7.7% (with a maximum of 50%) of mutants that are not detected by tests generated at the unit level; (3) CLING can detect integration faults coming from wrong assumptions about the usage of the callee class (32 for our subject systems) that remain undetected when using automatically generated unit-level test suites.

Design and implementation of a robust random number generator based on chaotic ring oscillators

In this paper, the design and implementation of a robust random number generator (RNG) based on chaotic ring oscillators is presented. The RNG output bits are generated through the chaotic sampling of chaotic waveform (CSCW) where the chaotic signals are obtained from two separate nodes of a chaotic ring oscillator (CRO). The proposed RNG is implemented on a FPGA (field-programmable gate array) combined with lumped elements on a breadboard circuit. The output bitstream of the proposed RNG passed the NIST 800-22 statistical randomness test suite without any need for post processing. To analyze the robustness of the CSCW method, a comparative analysis is conducted between chaos-based bit generation methods in terms of robustness against external interference. It is demonstrated that the proposed CSCW method ensures higher immunity of the RNG against external interference.

Designing a Pseudorandom Bit Generator With a Novel Five-Dimensional-Hyperchaotic System

Dynamic and non-linear systems are emerging as potential candidates for random bit generation. In this context, chaotic systems, which are both dynamic and stochastic, are particularly suitable. This paper introduces a new continuous chaotic system along with its corresponding implementation, which targets field-programmable gate array (FPGA). This chaotic system has five dimensions, which exhibit complex chaotic dynamics, thus enabling the utilization of chaotic signals in cryptography. A mathematical analysis is presented to demonstrate the dynamic characteristics of the proposed hyperchaotic system. A novel digital implementation of the proposed system is presented. Moreover, a data scrambling circuit is implemented to eliminate the bias effect and increase the randomness of the bitstream generated from the chaotic signals. We show that the proposed random bit generator has high randomness. The generated bits successfully pass well-known statistical randomness test-suites, i.e., NIST SP800-22, Diehard, and TestU01. The ready-to-use random bit generator is deployed on a Xilinx Zynq-7000 SoC ZC702 Evaluation Kit. Experimental results show that the proposed random bit generator can achieve a maximum throughput of 6.78 Gbps, which is over 3.6 times greater than state-of-the-art designs while requiring under 4% of the resources available on the targeted FPGA.

Block Cipher's Substitution Box Generation Based on Natural Randomness in Underwater Acoustics and Knight's Tour Chain.

The protection of confidential information is a global issue, and block encryption algorithms are the most reliable option for securing data. The famous information theorist, Claude Shannon, has given two desirable characteristics that should exist in a strong cipher which are substitution and permutation in their fundamental research on “Communication Theory of Secrecy Systems.” block ciphers strictly follow the substitution and permutation principle in an iterative manner to generate a ciphertext. The actual strength of the block ciphers against several attacks is entirely based on its substitution characteristic, which is gained by using the substitution box (S-box). In the current literature, algebraic structure-based and chaos-based techniques are highly used for the construction of S-boxes because both these techniques have favourable features for S-box construction but also various attacks of these techniques have been identified including SAT solver, linear and differential attacks, Gröbner-based attacks, XSL attacks, interpolation attacks, XL-based attacks, finite precision effect, chaotic systems degradation, predictability, weak randomness, chaotic discontinuity, and limited control parameters. The main objective of this research is to design a novel technique for the dynamic generation of S-boxes that are safe against the cryptanalysis techniques of algebraic structure-based and chaos-based approaches. True randomness has been universally recognized as the ideal method for cipher primitives design because true random numbers are unpredictable, irreversible, and unreproducible. The biggest challenge we faced during this research was how can we generate the true random numbers and how can true random numbers utilized for strengthening the S-box construction technique. The basic concept of the proposed technique is the extraction of true random bits from underwater acoustic waves and to design a novel technique for the dynamic generation of S-boxes using the chain of knight's tour. Rather than algebraic structure- and chaos-based techniques, our proposed technique depends on inevitable high-quality randomness which exists in underwater acoustics waves. The proposed method satisfies all standard evaluation tests of S-boxes construction and true random numbers generation. Two million bits have been analyzed using the NIST randomness test suite, and the results show that underwater sound waves are an impeccable entropy source for true randomness. Additionally, our dynamically generated S-boxes have better or equal strength, over the latest published S-boxes (2020 to 2021). According to our knowledge first time, this type of research has been conducted, in which natural randomness of underwater acoustic waves has been used for the construction of block cipher's substitution box.

Single photon randomness originating from the symmetric dipole emission pattern of quantum emitters

Quantum random number generation is a key ingredient for quantum cryptography and fundamental quantum optics and could advance Monte Carlo simulations and machine learning. An established generation scheme is based on single photons impinging on a beam splitter. Here, we experimentally demonstrate quantum random number generation solely based on the symmetric emission profile of a dipole aligned orthogonal to the laboratory frame. The demonstration builds on defect centers in hexagonal boron nitride that emit photons in random directions within the dipole emission profile and benefits from the ability to manipulate and align the emission directionality. We prove the randomness in correlated photon detection events making use of the NIST randomness test suite and show that the randomness remains for two independently emitting defect centers. The scheme can be extended to random number generation by coherent single photons with potential applications in solid-state based quantum communication at room temperature.

On the use of Egyptian fractions for stream ciphers

Within the scope of the mutual interference between modern number theory and chaos-based cryptography, and as it is well-known and already explored for the decimal or the continued fraction expansion of irrational numbers, interesting random-like behaviors seem to be hidden in Egyptian fraction expansions, thus suggesting new chaos-based encryption systems. In fact, at a practical level, and as will be shown through the present study, concatenation of involved denominators and binary expansion generally lead to pseudo-random streams which satisfactorily pass the NIST statistical test suite for randomness. Then, to a certain extent, and for cryptographic purposes, this can be considered as a new tool to complete the conventional class of already-in-use pseudo-random number generators. Some mathematical issues, however, have to be clarified, as for example the chaoticity of the process obtained after converting these denominators to fractional parts of a wandering sequence of real numbers in the unit interval. To the best of our knowledge, and from a cryptographic point of view, previous works on the subject are limited to statistical tests (and subsequent cryptographic analysis) of the resulting one-time pads or stream ciphers, but no rigorous study has been conducted to justify these methods within chaos theory. Considering Egyptian expansions as a working example and using the term “chaotic” in the sense of Devaney, this is what our proposal is aimed at in the present work.

A PSEUDORANDOM NUMBER GENERATOR WITH FULL CYCLE LENGTH BASED ON AUTOMATA COMPOSITIONS

In this paper a new Pseudorandom Number Generator based on compositions of abstract automata is presented. We show that it has full cycle with length of 2^128. It is also shown that the output satisfies the statistical requirements of the NIST randomness test suite.

Beyond Statistical Analysis in Chaos-Based CSPRNG Design

The design of cryptographically secure pseudorandom number generator (CSPRNG) producing unpredictable pseudorandom sequences robustly and credibly has been a nontrivial task. Almost all the chaos-based CSPRNG design approaches invariably depend only on statistical analysis. Such schemes designed to be secure are being proven to be predictable and insecure day by day. This paper proposes a design and instantiation approach to chaos-based CSPRNG using proven generic constructions of modern cryptography. The proposed design approach with proper instantiation of such generic constructions eventually results in providing best of both worlds that is the provable security guarantees of modern cryptography and passing of necessary statistical tests as that of chaos-based schemes. Also, we introduce a new coupled map lattice based on logistic-sine map for the construction of CSPRNG. The proposed pseudorandom number generator is proven using rigorous security analysis as that of modern cryptography and tested using the standard statistical testing suites. It is observed that the generated sequences pass all stringent statistical tests such as NIST, Dieharder, ENT, and TestU01 randomness test suites.

284.8-Mb/s Physical-Layer Cryptographic Key Generation and Distribution in Fiber Networks

Key distribution is a major challenge of secure communication. Computational approaches to key distribution are breached by quantum algorithms, while quantum key distribution (QKD) is an expensive, slow, and sophisticated solution. Secure key generation and distribution from unpredictable and inherent physical-layer properties of optical fiber channel is a classical, simple and cost-effective solution. However, the quasi-static nature of fiber channels dramatically limits the available key generation rate (KGR) to the order of ~kbit/s. Here we effectively accelerate the KGR by six orders of magnitude using a developed high-speed chaotic polarization scrambler (CPS) driven by digital chaos in fiber channels. An error-free KGR of 284.8 Mbit/s is experimentally demonstrated over a 24 km standard single-mode fiber (SSMF), where the generated key passes the random test suite. Moreover, we fully analyze the security mechanism and find that a strong asymmetry exists between legal and illegal users, ensuring a high-level of security against potential fiber-tapping attacks. This scheme provides a major step towards the practical implementation of the “one-time-pad” in secure data transmission over fiber networks.

An Empirical Comparison of Combinatorial Testing, Random Testing and Adaptive Random Testing

We present an empirical comparison of three test generation techniques, namely, Combinatorial Testing (CT), Random Testing (RT) and Adaptive Random Testing (ART), under different test scenarios. This is the first study in the literature to account for the (more realistic) testing setting in which the tester may not have complete information about the parameters and constraints that pertain to the system, and to account for the challenge posed by faults (in terms of failure rate). Our study was conducted on nine real-world programs under a total of 1683 test scenarios (combinations of available parameter and constraint information and failure rate). The results show significant differences in the techniques’ fault detection ability when faults are hard to detect (failure rates are relatively low). CT performs best overall; no worse than any other in 98 percent of scenarios studied. ART enhances RT, and is comparable to CT in 96 percent of scenarios, but its computational cost can be up to 3.5 times higher than CT when the program is highly constrained. Additionally, when constraint information is unavailable for a highly-constrained program, a large random test suite is as effective as CT or ART, yet its computational cost of test generation is significantly lower than that of other techniques.

The relation between Proportion test and Uniformity test in NIST SP800-22

NIST SP800-22 statistical test tool is one of the randomness test suites. It consists of 15 kinds of tests, and each test outputs the p-value for a sequence. Each test outputs multiple p-values when we test plural sequences. SP800-22 suggests to perform additional hypothesis tests for the multiple p-values, called the proportion test and the uniformity test, and judge the randomness of the tested sequences. To make a rational criterion for the two tests, the relation between the proportion test and the uniformity test is essential. In this paper, we derive the probability that both the proportion and uniformity tests simultaneously reject the null hypothesis. In the derivation process, we use a numerical method, but it is not a stochastic algorithm. Thus, we can ensure the properness of the derived value of the probability.

Constructing Test Suites for Real-Time Embedded Systems Under Input Timing Constraints

Testing of real-time embedded systems (RTESs) under input timing constraints is a critical issue. Models which can specify timing constraints have respective merits and demerits and test suites which can cover more input possibilities and detect more faults under input timing constraints are worthy of study. In this paper, clocked computation tree logic which is used to specify input timing constraints is presented. Neighbor covering arrays and parallel input time correlation test suites are introduced to test RTESs under serial and parallel input timing constraints. Three algorithms are described in generating test suites, respectively, and corresponding random testing-based algorithms which are used as baselines for comparison are introduced. Benchmarks with different configurations are conducted to evaluate the algorithms' performance. Three real-world RTESs are tested with the test suites described in this paper, respectively. The test results show that random testing may omit some neighbor input time point combinations as the randomness and increase test suite scales. This fact may lead to the omission of some faults and heavy costs. Therefore, the proposed test suites are more effective and efficient for testing RTESs under input timing constraints.

Practical True Random Number Generator Using CMOS Image Sensor Dark Noise

We present a true random number generator (TRNG) using dark noise of a CMOS image sensor. Because the proposed TRNG is based on the dark characteristics of the CMOS image sensor, it does not require any additional hardware, such as light source and optics, for providing true randomness. Therefore, it can be a promising solution for compact and low-cost mobile application. By using NIST SP 800-90B entropy assessment suite, we evaluate the min-entropy for the raw outputs of our original noise source and the final random numbers including post-processing as well. We also adopt NIST SP 800-22 statistical randomness test suite for the evaluation of the random numbers. The test results demonstrate that the generated random numbers pass all the statistical tests and have high entropy.

CSRO-Based Reconfigurable True Random Number Generator Using RRAM

In this paper, we propose a high-speed (kilohertz–megahertz), reconfigurable current starved ring oscillator (CSRO)-based true random number generator (TRNG) design. The proposed TRNG exploits the intradevice stochastic variations in resistive RAM switching parameters and random telegraph noise (RTN). We demonstrate the effect of RTN on the jitter of CSRO oscillations. We also propose a methodology to reconfigure the TRNG to generate new random numbers. The proposed 10-bit TRNG is validated by NIST test suite for randomness in the data stream. Energy/bit is 22.8 fJ for generation, and the speed of random data generation is 6 MHz. Security vulnerabilities and countermeasures of the proposed TRNG are also investigated.

A Sound Assessment of Test Suite Minimization Techniques

During software development, testing and re-testing occurs frequently to ensure that the software is working correctly before and after modifications. To carry out an effective testing process a test suite is created and executed to detect the faults in the existing code as well as in the modified code. The manual approach of test suite creation and execution is time consuming and labour intensive task as compared to automatically generated test data or test suite. The automatic test data generation is supposed to be an effective way, but a lot of redundant test cases are generated that increase the time, effort and cost of testing. Therefore, test suite minimization techniques are used to further minimize or reduce the number of test cases by selecting a subset from an initially random and large test suite to test the code before as well as after modification. In this study, a comprehensive analysis of the different test suite minimization techniques is presented in order to extend the existing studies and to propose new ideas in this direction.

True random bit generators based on current time series of contact glow discharge electrolysis

Random bit generators (RBGs) in today's digital information and communication systems employ a high rate physical entropy sources such as electronic, photonic, or thermal time series signals. However, the proper functioning of such physical systems is bound by specific constrains that make them in some cases weak and susceptible to external attacks. In this study, we show that the electrical current time series of contact glow discharge electrolysis, which is a dc voltage-powered micro-plasma in liquids, can be used for generating random bit sequences in a wide range of high dc voltages. The current signal is quantized into a binary stream by first using a simple moving average function which makes the distribution centered around zero, and then applying logical operations which enables the binarized data to pass all tests in industry-standard randomness test suite by the National Institute of Standard Technology. Furthermore, the robustness of this RBG against power supply attacks has been examined and verified.

Flexible Droplet Routing in Active Matrix–Based Digital Microfluidic Biochips

The active matrix (AM)-based architecture offers many advantages over conventional digital electrowetting-on-dielectric (EWOD) microfluidic biochips, such as the capability of handling variable-size droplets, more flexible droplet movement, and precise control over droplet navigation. However, a major challenge in choosing the routing paths is to decide when the droplets are to be reshaped depending on the congestion of the intended path, or split- and route sub droplets,and merging them at their respective destinations. As the number of microelectrodes in AM-EWOD chips is large, the path selection problem becomes further complicated. In this article, we propose a negotiation-guided flow based on routing of subdroplets that obviates the explicit need for deciding when the droplets are to be manipulated, yet fully utilizing the power of droplet reshaping, splitting, and merging them to facilitate their journey. The proposed algorithm reduces routing cost and provides more freedom in deadlock avoidance in the presence of multiple routing tasks by assigning certain congestion penalty for sibling subdroplets and fluidic penalty for heterogeneous droplets. Compared to existing techniques, it reduces latest arrival time by an average of 29% for several benchmark and random test suites. Furthermore, our method is observed to provide 100% routability of nets for all test cases, whereas existing and baseline routers fail to produce feasible solutions in many instances. We also propose a reliable mode droplet routing strategy where the number of unreliable splitting operations can be reduced by paying a small penalty on latest arrival time.