Random Dopant Fluctuation Effects Research Articles

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

Statistical analysis of the impact of charge traps in p-type MOSFETs via particle-based Monte Carlo device simulations

In this paper, statistical analysis of the static impact of charge traps on the drain current of p-type metal–oxide–semiconductor field-effect transistors is presented. The study was carried out by employing a 3-D particle-based Monte Carlo device simulator, which is capable of accounting for the interplay between charge traps and the random dopant fluctuation effect. It was observed that the impact of a single charged trap on the transistor’s on-current is strongly dependent on the trap position along the channel length, on trap depth into the gate oxide, and on the trap position along the channel width. The current deviation estimated from statistical simulations is shown to be exponentially distributed, in agreement with experimental data from the literature. Results are also compared with uniform channel theory predictions.

An ON-Current and Effective Drive Current Model for Nanowire MOSFETs with Random Dopant Fluctuations

We report a novel analytic model for the ON -current and effective drive current in nanowire MOSFETs considering the random dopant fluctuation effects. This model is derived from the basic drain current equation considering RDF in the channel region of the device. The model makes use of appropriate voltage relations to be applied in the oxide-interface boundary conditions, and is found to be in excellent agreement with TCAD simulations of the device considering RDF effects.

Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Analysis and Modeling of Current Mismatch in Laterally Nonuniform MOSFETs

We present an analytical modeling approach for drain current ( ${I}_{D}$ ) mismatch in lateral nonuniformly doped (NUD) MOSFETs. The model uses the carrier number fluctuation theory to include the effect of random dopant fluctuations (RDFs) on inversion charge fluctuation (ICF) in different operating regions. Our analysis shows that the conventional models for uniformly doped device underestimate the ${I}_{D}$ mismatch by one-to-two orders of magnitude at low gate voltages in NUD devices. We have also considered the effect of RDF on mobility fluctuation (MF), which shows its significant role in strong inversion (SI). To investigate the physical mechanism leading to such a behavior, extensive technology computer-aided design simulations are performed for various conditions of bias, doping profiles, and temperature. Using the impedance field method to calculate the relative contributions of RDF to ICF and MF, we show that our model can successfully capture the drain current mismatch across subthreshold to SI in the NUD device.

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High-dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time-independent process-induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in BTI degradation. Since time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time-zero variability on all of these effects simultaneously. Accordingly, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000nm2) in 30nm technology, we observe significant effects of Random Dopant Fluctuation (RDF) on BTI-induced variability (σΔVth). In addition, circuit analysis reveals similar trend in performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered in variation-tolerant circuit design.

A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism

For the first time, a distinctive approach based on electrically doped concept is used for the formation of novel double gate tunnel field effect transistor (TFET). For this, the initially heavily doped n+ substrate is converted into n+-i-n+-i (Drain-Channel-Source) by the selection of appropriate work functions of control gate (CG) and polarity gate (PG) as 4.7 eV. Further, the formation of p+ region for source is performed by applying −1.2 V at PG. Hence, the structure behave like a n+-i-n+-p+ gated TFET, whereas, the control gate is used to modulate the effective tunneling barrier width. The physical realization of delta doped n+ layer near to source region is a challenging task for improving the device performance in terms of ON current and subthreshold slope. So, the proposed work will provide a better platform for fabrication of n+-i-n+-p+ TFET with low cost and suppressed random dopant fluctuation (RDF) effects. ATLAS TCAD device simulator is used to carry out the simulation work.

Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node

This paper presents a FinFET-based static 1-bit full adder cell that helps to recover the huge penalty in performance, while staying quite close to the minimum energy point. The proposed design offers higher computing speed (by 7.96×) and lower energy (by 5.86×), lower energy-delay product (EDP) (by 21.08×) at the expense of higher power dissipation (by 1.36×) compared to its MOSFET counterpart. It proves its robustness against process variations by featuring tighter spread in power distribution (by 3.20×), in delay distribution (by 4.70×), in PDP (power-delay product) distribution (by 3.35×) and in EDP distribution (by 3.14×) compared to its MOSFET counterpart. The proposed design achieves these improvements due to employment of new FinFET technology in the full adder design. Multi-gate devices in this technology are less affected by random dopant fluctuation (RDF) and short-channel effects such as threshold voltage rolloff, drain-induced barrier lowering (DIBL), etc. To establish that our design is better this paper analyzes five more 1-bit full adder cells and compares them with the proposed design in terms of power, delay and PDP. We perform simulation using 32-nm Predictive Technology Model (PTM) parameters on SPICE.

Variability study of Si nanowire FETs with different junction gradients

Random dopant fluctuation effects of gate-all-around Si nanowire field-effect transistors (FETs) are investigated in terms of different diameters and junction gradients. The nanowire FETs with smaller diameters or shorter junction gradients increase relative variations of the drain currents and the mismatch of the drain currents between source-drain and drain-source bias change in the saturation regime. Smaller diameters decreased current drivability critically compared to standard deviations of the drain currents, thus inducing greater relative variations of the drain currents. Shorter junction gradients form high potential barriers in the source-side lightly-doped extension regions at on-state, which determines the magnitude of the drain currents and fluctuates the drain currents greatly under thermionic-emission mechanism. On the other hand, longer junction gradients affect lateral field to fluctuate the drain currents greatly. These physical phenomena coincide with correlations of the variations betwe...

The effect of random dopant fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents.

Hybrid methodology to model random dopant fluctuations in low doped FinFETs

A hybrid approach to model the effect of random dopant fluctuations in low doped FinFETs is proposed. Existing Monte Carlo and atomistic approaches are found to be inadequate to capture device variability correctly when applied independently. Instead a hybrid methodology which uses an atomistic approach in low doped regions and Monte Carlo everywhere else is developed. The hybrid approach is shown to capture the threshold voltage variability adequately. Comparison with analytical results for planar MOSFETs shows an excellent agreement and establishes the validity of the approach. The results suggest that accurate modeling of low doped regions is essential to be able to estimate variability correctly.

Upper/lower-side random dopant fluctuation on 16-nm-gate HKMG bulk FinFET

In this work, we for the first time classify dopants that exist near the source/drain side or the upper/lower side of silicon fin and explore the impact of random dopants' (RDs) position on devices' DC characteristic. The effects of random dopant fluctuation (RDF) on the performance of 16–nm–gate HKMG bulk FinFET are studied by using experimentally validated three–dimensional RDF device simulation. The dopants near the source side or the upper fin would induce large barrier for electrons, so the threshold voltage (Vth) will be increased in n–type HKMG bulk FinFET devices which have more dopants on the source side or the upper fin. In addition, the upper–fin's dopants are discovered to have larger influence on the profile of energy band. Moreover, the issue about Vth's fluctuation on both the planar MOSFET and the bulk FinFETs with different aspect ratios (AR) is studied. The higher–AR HKMG bulk FinFET devices have relatively smaller Vth's variation induced by RDF.

Investigation of the random dopant fluctuations in 20-nm bulk MOSFETs and silicon-on-insulator FinFETs by ion implantation Monte Carlo simulation

In this paper, we proposed a simulation approach for studying the random dopant fluctuation (RDF) effects in the nanoscale MOSFETs using only the TCAD tools. We use this approach to simulate the RDF effects in the 20-nm gate-length bulk MOSFETs, silicon-on-insulator (SOI) single-gate (SG) and triple-gate (TG) FinFETs for demonstration. This approach utilises the stochastic nature of the Monte Carlo (MC) simulation of ion implantation to capture the RDF phenomena in the devices. The simulation results show that the standard deviation of the threshold voltage ( σV T ) is approximately proportional to the cube root of the channel doping concentration for the simulated conventional bulk MOSFETs. For the SOI SG and TG FinFETs, the σV T increases much less than that of the conventional bulk MOSFETs as the channel doping concentration increases. Besides, the σ V T of the SOI TG FinFETs show about 30–40% reductions comparing to those of the SOI SG FinFETs. The average of the MC simulation results agrees with the implant table simulation results. The reasonable simulation results verify the validity of this TCAD simulation scheme for the RDF study.

터널링 전계효과 트랜지스터의 불순물 분포 변동 효과

3차원 시뮬레이션을 이용하여 터널링 전계효과 트랜지스터(TFET)의 불순물 분포 변동(RDF) 효과에 대해 살펴보았다. TFET의 RDF 효과는 매우 낮은 바디 도핑 농도 때문에 많이 논의되지 않았다. 하지만 본 논문에서는 임의로 생성되고 분포되는 소스 불순물이 TFET의 문턱전압 (<TEX>$V_{th}$</TEX>)과 드레인 유기 전류 증가 (DICE), 문턱전압이하 기울기 (SS)의 변화를 증가시킴을 발견하였다. 또한, TFET의 RDF 효과를 감소시킬 수 있는 몇 가지 방법을 제시하였다. The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage (<TEX>$V_{th}$</TEX>), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage

In order to achieve ultra-low power (ULP), ICs are being designed for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ≤ 0.5 V. At these low voltages, random dopant fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the global corner delay. Moreover, the probability density function (PDF) of this stochastic delay can be highly non-Gaussian. In order to predict the statistical impact of RDF-induced local variations on logic timing, it is necessary to incorporate these effects into a timing closure methodology. This paper presents a computationally efficient methodology for stochastic characterization of standard cell li- braries at low voltage, where the cell delay is a nonlinear function of the transistor random variables (RVs), and the resulting cell delay has a non-Gaussian PDF. It also presents a computation- ally efficient methodology for computing any point on the PDF of a timing path (TP) delay, in the case where cell delays are non-Gaussian. The method is called nonlinear operating point analysis of local variation (NLOPALV). The general NLOPALV theory is developed. It is applied to cell library characterization, and the accuracy of the NLOPALV approach is validated by comparison to Monte Carlo simulation. NLOPALV is also applied to timing path analysis on a 28 nm DSP IC. The approach has been implemented using commercial CAD tools, and integrated into a commercial IC design flow. The NLOPALV approach gives timing results that are within 5% accuracy compared to Monte Carlo analysis at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.5 V. This compares to errors on the order of 50% when the Gaussian approximation is used.

Impact of Random Dopant Fluctuation Effect on Surrounding Gate MOSFETs: From Atomic Level Simulation to Circuit Performance Evaluation

This paper investigates the impact of random dopant fluctuation effect on surrounding gate MOSFET, from atomic statistical simulation of device to circuit performance evaluation. The doping profile is generated by an analysis of each lattice atom and then the threshold voltage variation is obtained by device Drift-Diffusion simulation. Then the circuit performance evaluation is performed by feeding the result into a surrounding-gate MOSFET model. It is shown that a significant fluctuation in threshold voltage is due to the decreasing volume. The circuit simulation results also reveal that a surrounding gate MOSFET based 6-T SRAM presents a promising resistibility to noise disturbance.

Analysis and optimization of current sensing circuit for deep sub-micron SRAM

A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented. It investigates the impact of transistor size, falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit. On this basis, we present a final optimization to improve the reliability of current sense amplifier. Under 90 nm process, simulation shows that failure probability of current sensing circuit can be reduced by 80% after optimization compared with the normal situation and the delay time only increases marginally.

Static Analysis of Random Telegraph Noise in a 45-nm Channel Length Conventional MOSFET Device: Threshold Voltage and ON-Current Fluctuations

In this paper, we investigate the threshold voltage and ON-current fluctuations due to the presence of charged traps located in the middle portion of the channel when the trap is moved from the source end to the drain end of the channel in a 45-nm technology node device with an effective channel length of 35 nm. Our thorough investigations suggest that the threshold voltage fluctuation and its standard deviation are much larger than the ON-current fluctuation since in the ON-state screening effectively reduces the strength of the trap Coulomb potential, which is not the case in the OFF-state. We believe that this is a first study that simultaneously investigates the effects of random dopant and random telegraph noise fluctuations that utilizes particle-based device simulators that correctly account for the long-range and the short-range Coulomb interaction. Unique feature of the approach is the proper incorporation, in a self-consistent manner, of the short-range Coulomb interaction via the real-space molecular dynamics routine. Indeed, Vasileska has pioneered this technique back in 1996. We also find that studies that do not account for the short-range Coulomb interaction correctly miss important feature that the threshold voltage standard deviations are not independent upon the position of the trap in the channel but are strongly correlated with it when the trap is located in the middle section of the source end of the channel. This suggests that an approach that correctly accounts for the short-range Coulomb interaction is a must when modeling either random dopant or random trap fluctuations in both the threshold voltage and the ON-current.