Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node

Abstract

This paper presents a FinFET-based static 1-bit full adder cell that helps to recover the huge penalty in performance, while staying quite close to the minimum energy point. The proposed design offers higher computing speed (by 7.96×) and lower energy (by 5.86×), lower energy-delay product (EDP) (by 21.08×) at the expense of higher power dissipation (by 1.36×) compared to its MOSFET counterpart. It proves its robustness against process variations by featuring tighter spread in power distribution (by 3.20×), in delay distribution (by 4.70×), in PDP (power-delay product) distribution (by 3.35×) and in EDP distribution (by 3.14×) compared to its MOSFET counterpart. The proposed design achieves these improvements due to employment of new FinFET technology in the full adder design. Multi-gate devices in this technology are less affected by random dopant fluctuation (RDF) and short-channel effects such as threshold voltage rolloff, drain-induced barrier lowering (DIBL), etc. To establish that our design is better this paper analyzes five more 1-bit full adder cells and compares them with the proposed design in terms of power, delay and PDP. We perform simulation using 32-nm Predictive Technology Model (PTM) parameters on SPICE.