Design of hybrid full adder in deep subthreshold region for ultralow power applications

Abstract

This paper proposes a 10T hybrid 1-bit full adder circuit at 16-nm technology node in deep subthreshold region for ultralow-power applications. The proposed design is hybrid of MOSFET and CNFET (Carbon Nanotube Field Effect Transistor). It exhibits lower power dissipation compared to its full-CMOS version. The proposed hybrid design achieves 0.96x (1.02x), 1.06x (0.99x), 1.06x (0.99x) improvement in average power (average power variability), power-delay product (PDP variability), energy-delay product (EDP variability) respectively compared to its full-CMOS version. To verify the versatility of the proposed hybrid 1-bit full adder, we have employed it to design a 4-bit ripple carry full adder and observed that this design consumes ultralow power compared to its full CMOS version. The hybrid 4-bit adder achieves 1.05x (1.01x), 1.05x (1.01x), 1.05x (1.01x) improvement in average power (average power variability), power-delay product (PDP variability), energy-delay product (EDP variability) respectively compared to its full-CMOS version.