Parametric analysis of a hybrid 1-bit full adder in UDSM and CNTFET technology

Abstract

The basic arithmetic operation used in many VLSI circuits is addition, therefore reduction in power dissipation of 1-bit adder cell will improve the performance of most of electronic devices. Carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have proposed CNTFETs for designing a 1-bit Hybrid full adder circuit, from which power, delay and power delay products are calculated. This paper also presents power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed and power consumption. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existing standard full adders and the proposed hybrid full adders [1] are designed and showed with better result comparison. This paper describes how the proposed hybrid full adders [1] are better in contrast to the standard full adders and also analyses how the standard full adders are not giving faithful results. The circuit was implemented using Cadence Virtuoso tools in 180, 90, 45nm and 32nm technology. We have tested these circuit for a supply of 1.8V for 180nm, 1.2V for 90nm, 1V for 45nm and 0.8V for 32nm CNTFET technology.