Random Access Memory Technology Research Articles

ReRAM: History, Status, and Future

This article reviews the resistive random-access memory (ReRAM) technology initialization back in the 1960s and its heavily focused research and development from the early 2000s. This review goes through various oxygen/oxygen vacancy and metal-ion-based ReRAM devices and their operation mechanisms. This review also benchmarks the performance of various oxygen/oxygen vacancy and metal-ion-based ReRAM devices with general trend drawn. Being a semiconductor memory and storage technology, the commercialization attempts for both stand-alone mass storage/storage-class memory and embedded nonvolatile memory are also reviewed. Looking toward the coming era, the potential of using ReRAM technology to improve machine learning efficiency is discussed.

Size-Dependent Switching Properties of Spin-Orbit Torque MRAM With Manufacturing-Friendly 8-Inch Wafer-Level Uniformity

We have developed a manufacturing-friendly spin-orbit torque magnetic random access memory (SOT-MRAM) technology in CMOS compatible 8-inch fab process. The proposed SOT-MRAM process technology resolves etching non-uniformity and reduction of high resistivity heavy-metal nanowire resistance issues. Besides, we present device size-dependent switching current threshold in the proposed SOT-MRAM cell structure. To realize the potential of our fabricated SOT-MRAM, wafer-level uniformity, cycling and temperature dependence SOT switching have been comprehensively investigated. Furthermore, the thermal stability factor (△) was calculated from temperature-dependence SOT switching to fulfill the thermal stability criteria, i.e., > 10 years of this emerging SOT-MRAM technology.

A Novel Compound Synapse Using Probabilistic Spin–Orbit-Torque Switching for MTJ-Based Deep Neural Networks

Analog electronic nonvolatile memories mimicking synaptic operations are being explored for the implementation of neuromorphic computing systems. Compound synapses consisting of ensembles of stochastic binary elements are alternatives to analog memory synapses to achieve multilevel memory operation. Among the existing binary memory technologies, magnetic tunneling junction (MTJ)-based magnetic random access memory (MRAM) technology has matured to the point of commercialization. More importantly for this work, stochasticity is natural to the MTJ switching physics, e.g., devices referred to as p-bits that mimic binary stochastic neurons. In this article, we experimentally demonstrate a novel compound synapse that uses stochastic spin–orbit-torque (SOT) switching of an ensemble of nanomagnets that are located on one shared spin Hall effect (SHE) material channel, i.e., tantalum. By using a properly chosen pulse scheme, we are able to demonstrate linear potentiation and depression in the synapse, as required for many neuromorphic architectures. In addition to this experimental effort, we also performed circuit simulations on an SOT-MRAM-based $784\times 200\times 10$ deep belief network (DBN) consisting of p-bit-based neurons and compound synapses. MNIST pattern recognition was used to evaluate the system performance, and our findings indicate that a significant reduction in recognition error rates can be achieved by improving the linearity of the potentiation and depression curves using an incremental pulse scheme.

Independent Control of Antiparallel- and Parallel-State Thermal Stability Factors in Magnetic Tunnel Junctions for Telegraphic Signals With Two Degrees of Tunability

Magnetic tunnel junctions (MTJs) with low thermal stability at room temperature have been proposed as read units in beyond CMOS computing architectures including stochastic computing unit and probabilistic-bit (p-bit). Networks of multiple interconnected MTJs may face challenges due to potential device-to-device variations in thermal stability from design targets. Recently, we generated tunable telegraphic signals using a thermally stable MTJ through proper control over an external bias field and a dc voltage bias, where we showed that the average dwell times in the antiparallel (AP) and parallel states could be tuned separately. The implication for this method for p-bit designs is that it allows for p-bits to be compatible with the state-of-the-art magnetoresistive random-access memory (MRAM) technology and introduces a second degree of tunability to the input–output characteristics of the device. In this article, we expand on this method in two important ways. First, we demonstrate the applicability of our method to p-bit designs by modeling the transfer function using the existing p-bit models. Our results indicate that the transfer function can be adjusted with slight modifications to the bias field, which allows for the possibility of p-bit circuits capable of on-chip corrections against device-to-device variations in their thermal stabilities. Second, we identify the physical mechanisms that allow for two degrees of tunability in the output signal, which is explained through the Neel–Brown model. This article provides both applicability and predictability to the dual-biasing method.

Recent advances in the understanding of high-kdielectric materials deposited by atomic layer deposition for dynamic random-access memory capacitor applications

Abstract

Out-of-Plane Focusing Grating Couplers for Silicon Photonics Integration With Optical MRAM Technology

We present the design methodology and experimental characterization of compact out-of-plane focusing grating couplers for integration with magnetoresistive random access memory technology. Focusing grating couplers have recently found attention as layer-couplers for photonic-electronic integration. The components we demonstrate are designed for a wavelength of 1550 nm, fabricated in a standard 220 nm SOI photonic platform and optimized given the fabrication restrictions for standard 193-nm UV lithography. For the first time, we extend the design based on the phase matching condition to a two-dimensional (2-D) grating design with two optical input ports. We further present the experimental characterization of the focusing behaviour by spatially probing the emitted beam with a tapered-and-lensed fiber and demonstrate the polarization controlling capabilities of the 2-D FGCs.

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance , and write failure . Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In this paper, we propose a system-level framework for reliability exploration and characterization of errors’ behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the intercorrelation of the error types including RF, read disturbance, and write failure as well as the dependency of error rates to workloads’ behavior and process variations (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by PVs in STT-MRAM cells. To take the effects of system workloads and PVs into account, we implement the error types in gem5 full-system simulator. The experimental results using a comprehensive set of multiprogrammed workloads from SPEC CPU2006 benchmark suite on a quad-core processor show that the total error rate in a shared STT-MRAM LLC varies by 32.0× for different workloads. A further 6.5× vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs. The proposed analytical and empirical studies can significantly help system architects for efficient utilization of error mitigation techniques and designing highly reliable and low-cost STT-MRAM LLCs.

Nanoscale 3D Stackable Ag-Doped HfOx-Based Selector Devices Fabricated through Low-Temperature Hydrogen Annealing.

Electrochemical metallization-based threshold switching devices with active metal electrodes have been studied as a selector for high-density resistive random access memory (RRAM) technology in crossbar array architectures. However, these devices are not suitable for integration with three-dimensional (3D) crossbar RRAM arrays due to the difficulty in vertical stacking and/or scaling into the nanometer regime as well as the asymmetric threshold switching behavior and large variation in the operating voltage. Here, we demonstrate bidirectional symmetric threshold switching behaviors from a simple Pt/Ag-doped HfOx/Pt structure. While fabricating the Pt/Ag-doped HfOx/Pt film using a 250 nm hole structure, filaments composed of Ag nanoclusters were constructed through a low-temperature (∼200 °C) hydrogen annealing process where the shape of the film in a nanoscale via a hole structure was maintained for integration with 3D stackable crossbar RRAM arrays. Finite Ag filament paths in the HfOx layer led to uniform device-to-device performances. Moreover, we observed that the hydrogen annealing process reduced the delay time through the reduction of the oxygen vacancies in the HfOx layer. Consequently, the proposed Pt/Ag-doped HfOx/Pt-based nanoscale selector devices exhibited excellent performance of high selectivity (∼105), ultralow OFF current (∼10 pA), steep turn-on slope (∼2 mV/decade), and short delay time (3 μs).

Efficient compute node-local replication mechanisms for NVRAM-centric data structures

The long-awaited nonvolatile random-access memory technology NVRAM is finally publicly available on the market and requires significant changes to the architecture of in-memory database systems. Since such hybrid DRAM–NVRAM database systems may be able to keep the primary data solely persistent in the NVRAM, efficient replication mechanisms need to be considered to prevent base data losses and to guarantee high availability in case of various persistent memory failures. In this article, we argue for a software-based replication approach and present compute node-local mechanisms to provide the building blocks—generally available for most platforms—for an efficient NVRAM replication with a low latency and minimal throughput penalty. Within our evaluation, based on both real NVRAM hardware and DRAM-backed emulation, we measured up to 10$$\times $$ less overhead for our optimized replication mechanisms compared to the basic replication mechanism of the Intel persistent memory development kit PMDK. Finally, we present a lightweight switching approach for enabling the adaptive online selection of the best replication mechanism for a given situation.

Resistive Random Access Memory (ReRAM)

Resistive Random-Access Memory (ReRAM) technology has been viewed as one of the most reliable non-volatile memories that have are emerging in markets. In this research paper, the revolution of ReRAM will be analyzed. Also, the paper will also review the recent progress in the technological development of ReRAM. The performance parameters of these non-volatile memories such as their operating voltage, operation speed, resistance ratio, endurance, retention time, device yield, and multilevel storage will be analyzed. Integration and reliability of Re-RAM in the practical level is compared with other types of memories. Challenges faced by users of ReRAM are addressed in regards to technological fallbacks among other challenges. Finally, the future research on the ReRAM will be analyzed.

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)

Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capabi...

Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons

Magnetoresistive random access memory (MRAM) technologies with thermally unstable nanomagnets are leveraged to develop an intrinsic stochastic neuron as a building block for restricted Boltzmann machines (RBMs) to form deep belief networks (DBNs). The embedded MRAM-based neuron is modeled using precise physics equations. The simulation results exhibit the desired sigmoidal relation between the input voltages and probability of the output state. A probabilistic inference network simulator (PIN-Sim) is developed to realize a circuit-level model of an RBM utilizing resistive crossbar arrays along with differential amplifiers to implement the positive and negative weight values. The PIN-Sim is composed of five main blocks to train a DBN, evaluate its accuracy, and measure its power consumption. The MNIST dataset is leveraged to investigate the energy and accuracy tradeoffs of seven distinct network topologies in SPICE using the 14nm HP-FinFET technology library with the nominal voltage of 0.8V, in which an MRAM-based neuron is used as the activation function. The software and hardware level simulations indicate that a 784× 200× 10 topology can achieve less than 5% error rates with ∼400pJ energy consumption. The error rates can be reduced to 2.5% by using a 784× 500× 500× 500× 10 DBN at the cost of ∼10× higher energy consumption and significant area overhead. Finally, the effects of specific hardware-level parameters on power dissipation and accuracy tradeoffs are identified via the developed PIN-Sim framework.

Newly developed process integration technologies for highly reliable 40 nm ReRAM

We have developed a 40 nm resistive random access memory (ReRAM) technology embedded in a foundry-standard CMOS process for low-power applications. Excellent reliability was achieved in 8 Mbit, 40 nm ReRAM: 100 k cycles and 10 year retention at 85 °C after 10 k cycles were demonstrated for resistive switching element (RSE) process technologies and filament characterization methods. Regarding process technologies for 40 nm ReRAM, we tackled four forms of integration. First, we experimented with RSE etching, to optimize damage-less etching of RSE, metal and dielectric. Second, we tried to maintain the back end of line process/parameter compatibility with the standard 40 nm CMOS process. Third, we developed our own techniques to form RSE cells that are protected against extra free oxygen to realize design flexibility. Fourth, we optimized the components of the high-resistivity layer (Ta2O5), specifically film density, and confirmed that it is possible to achieve both ease of occurrence of formation and reduced non-uniformity of the resistance values corresponding to the high resistive state.

A spill data aware memory assignment technique for improving power consumption of multimedia memory systems

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation. This study describes a compiler optimization technique to overcome such disadvantages of a nonvolatile memory component in hybrid cache memories. A hybrid cache is proposed to overcome the disadvantages using a compiler. Specifically, to minimize the number of write operations for nonvolatile memory, we present a data replacement technique that considers the locations of the register spill data. Many portions of the memory accesses are yielded by the spill data of a register allocator in an optimizing compiler. Such spill data can be partially removed using a recalculation method. Thus, we implemented an optimization technique that rearranges the data placement with recalculation to minimize the write instructions on the nonvolatile memory. Our experimental results show that the proposed technique can reduce the average number of spill codes by 20%, and improves the energy consumption by 20.2% on average.

Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors

Ultra-low power processors designed to work at very low voltage are the enablers of the internet of things (IoT) era. Their internal memories, which are usually implemented by a static random access memory (SRAM) technology, stop functioning properly at low voltage. Some recent commercial products have replaced SRAM with embedded memory (eDRAM), in which stored data are destroyed over time, thus requiring periodic refreshing that causes performance loss. This article presents a queuing-based opportunistic refreshing algorithm that eliminates most if not all of the performance loss and is shown to be optimal. The queues used for refreshing miss refreshing opportunities not only when they are saturated but also when they are empty, hence increasing the probability of performance loss. We examine the optimal policy for handling a saturated and empty queue, and the ways in which system performance depends on queue capacity and memory size. This analysis results in a closed-form performance expression capturing read/write probabilities, memory size and queue capacity leading to CPU-internal memory architecture optimization.

A Two-Dimensional Associative Processor

Computing based on traditional approaches has hit its limits in terms of scalability and power consumption. For this reason, new computing paradigms have started to emerge that aim to perform operations directly in-memory to eliminate data movement costs. Even though traditional in-memory processor architectures together with emerging semiconductor technologies show promise for improving the efficiency of parallel computing, they lack some vital requirements such as flexibility and sequential execution. In this paper, a novel 2-D in-memory computing architecture is proposed. The proposed associative processing architecture is implemented by both CMOS/static random-access memory and ReRAM technologies and employed as an accelerator. As proven by circuit simulations and comparisons on a variety of benchmarks from different domains, the proposed architecture facilitates very efficient in-memory parallel computing together with a high degree of flexibility that results in faster running time in fundamental benchmarks.

Two-terminal spin–orbit torque magnetoresistive random access memory

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is an attractive alternative to current random access memory technologies due to its non-volatility, fast operation and high endurance. STT-MRAM does though have limitations including the stochastic nature of the STT-switching and a high critical switching current, which makes it unsuitable for ultrafast operation at nanosecond and sub-nanosecond regimes. Spin-orbit torque (SOT) switching, which relies on the torque generated by an in-plane current, has the potential to overcome these limitations. However, SOT-MRAM cells studied so far use a three-terminal structure in order to apply the in-plane current, which increases the size of the cells. Here we report a two-terminal SOT-MRAM cell based on a CoFeB/MgO magnetic tunnel junction pillar on an ultrathin and narrow Ta underlayer. In this device, an in-plane and out-of-plane current are simultaneously generated upon application of a voltage, and we demonstrate that the switching mechanism is dominated by SOT. We also compare our device to a STT-MRAM cell built with the same architecture and show that critical write current in the SOT-MRAM cell is reduced by more than 70%.

(Invited) Resistive Memories (RRAM) Variability: Challenges and Solutions

IntroductionResistive random access memory (RRAM) technologies have experienced an increasing interest as next generation non-volatile memory devices. Thanks to their promising characteristics, RRAM are believed to become a good choice for Storage Class Memory (SCM) [1-3]. Indeed, nowadays, due to popularity of cloud storage and mobile devices, it is urgent to develop lower energy consuming devices with high speed, high density and low cost. On the other hand, as they can be integrated in the BEOL of CMOS logic, they are strongly envisaged for future embedded memory generation [4-5]. RRAM working principle is based on the reversible formation and dissolution of a conductive filament in a resistive layer, resulting from oxygen vacancies generation and diffusion (OxRAM) or dissolution of an active electrode (CBRAM). As filament formation and dissolution is governed by stochastic mechanisms, RRAM features have to be described by statistic laws, and variability has to be carefully considered for RRAM reliability evaluation before industrialization could be envisaged. In this work, we address Resistive RAM (RRAM) variability. To this aim, we investigate various classes of RRAM (Oxide RAM and Conductive Bridging RAM), integrated on kb 1T1R arrays. Impact of variability is evaluated and discussed for various RRAM features: window margin, switching speed, consumption, retention and endurance. Solutions are proposed in order to improve overall RRAM performances. Results and discussionFirst, we present a general overview of RRAM characteristics, and investigate how performances are correlated. In particular, we show that window margin, endurance and retention are linked. Using electrical characterization combined with atomistic calculations, we demonstrate that the tradeoff is associated to the ion migration energy barrier of the species constituting the conductive filament, and we propose guidelines to optimize RRAM material stack depending on the targeted application. Then we deeply investigate variability, and we propose solutions to improve RRAM performances. Window margin variability – We describe RRAM resistance distributions for high and low resistive states and quantify how resistance dispersion affects RRAM window margin, and impacts maximum memory array size. Optimized programming schemes are proposed to reduce resistance dispersion and enlarge window margin. Consumption and speed – Variability has an impact on RRAM consumption and speed. Indeed, as RRAM switching time is dispersed, long programming pulses may be required to program all the array of a large memory matrix. In order to improve RRAM speed and consumption, Ramp Voltage Stress (RVS) is proposed to program the memory instead of Constant Voltage Stress (CVS) method. Voltage increase in RVS gradually increases programming strength, reducing impact of intrinsic RRAM switching time dispersion. Retention variability – Filament dissolution in the resistive layer is follows a stochastic behavior, leading to dispersion of memory retention time. In order to improve RRAM retention, we propose to reduce the energy provided to the system during programming modes, reducing ion migration rate and improving RRAM stability during bake. Endurance variability – We experimentally demonstrate that RRAM maximum number of cycles follows a log normal distribution law. Maximum endurance can be described using physics of dielectric breakdown. We investigate how SET and RESET programming conditions can affect RRAM endurance statistics. Then we propose optimized programming schemes to reduce electrical stress applied to the dielectrics, improving endurance, but maintaining sufficient RRAM window margin.

A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM

The 3-D vertical array architecture is considered to be a promising technology for emerging nonvolatile memories. But in 3-D vertical emerging nonvolatile memories, planar parasitic elements, vertical parasitic elements, and the sneak currents of the half-selected memory cells result in the delay of the read operation and read errors. This paper refers to the case of the 3-D vertical resistive switching random access memory (RRAM) technology. A read scheme, the memory core design, and the read path are proposed or analyzed. The factors that affect the read operation are concluded. A changing-reference parasitic-matching sensing circuit is, therefore, proposed. In the proposed circuit, the reference side and the read side share similar sneak currents and read paths. Simulated in a 40-nm CMOS process, the sensing time of 128-Mb 3-D vertical RRAM is 8.54 ns compared to the conventional 34.26 ns. Monte Carlo simulations show a 130.21-ns worst sensing time compared to the conventional 401.95 ns. The read errors are reduced by 100% and 95.31% under the regular and the worst RRAM resistance, respectively.

MemSens: Memristor-Based Radiation Sensor

Resistive random-access memory (RRAM) technology has been gaining importance due to scalability, low power, non-volatility, and the ability to perform in-memory computing. The RRAM sensing applications have also emerged to enable single RRAM technology platforms which include sensing, data storage, and computing. This paper reports on sol-gel drop coated low-power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> -thick Ag/TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Cu memristor, named MemSens, developed for radiation sensing. MemSens exhibits a bipolar memristive switching behavior within a small voltage window, ranging up to +0.7 V for the turn-ON, and down to −0.2 V for the turn-OFF. Under these operating conditions, MemSens has 67% less switching voltage, 20% drop in ON switching current, 75% reduced active area and > 3x improved device endurance, compared to the best characteristics reported in the literature for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> -thick memristors. The device is tested under direct exposure to ionizing Cs-137 662keV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays, during which a significant increase in the electrical conductivity of the device is observed. MemSens circuit is proposed to allow a relatively real time and cost-effective radiation detection. This provides a first insight to the advancement of reliable memristors that could potentially be deployed in future low-power radiation sensing technologies for medical, personal protection, and other field applications.