Abstract
We have developed a manufacturing-friendly spin-orbit torque magnetic random access memory (SOT-MRAM) technology in CMOS compatible 8-inch fab process. The proposed SOT-MRAM process technology resolves etching non-uniformity and reduction of high resistivity heavy-metal nanowire resistance issues. Besides, we present device size-dependent switching current threshold in the proposed SOT-MRAM cell structure. To realize the potential of our fabricated SOT-MRAM, wafer-level uniformity, cycling and temperature dependence SOT switching have been comprehensively investigated. Furthermore, the thermal stability factor (△) was calculated from temperature-dependence SOT switching to fulfill the thermal stability criteria, i.e., > 10 years of this emerging SOT-MRAM technology.
Highlights
The magnetic random access memory (MRAM) based on magnetic tunnel junction (MTJ) storage devices, which consists of two ferromagnetic layers separated by a magnetic insulating barrier layer has emerged as very promising candidate to replace the traditional CMOS-based memory technology [1]–[3]
The SOT-MRAM cell consisting of Ta/CoFeB/MgO/CoFeB/CoFe/Ru/CoFe/PtMn/ Ru/Ta multilayer film stacks were deposited by an ultra-high vacuum magnetron sputtering system on a thermally oxidized 8-inch Si substrate at room temperature (RT)
The magnetic properties of the blanket multilayer film stacks prepared for SOT-MRAM devices were analyzed using a vibrating sample magnetometer (VSM) with a maximum field of 1.0 T at RT
Summary
The magnetic random access memory (MRAM) based on magnetic tunnel junction (MTJ) storage devices, which consists of two ferromagnetic layers separated by a magnetic insulating barrier layer has emerged as very promising candidate to replace the traditional CMOS-based memory technology [1]–[3]. The spin-transfer torque magnetic random access memory (STT-MRAM) has attracted great attention because of its CMOS compatibility, excellent nonvolatility, high writing and reading speed, and zero leakage power [4]–[9]. The STT-MRAM cell is a two-terminal device, the current flows through the tunnel barrier of the cell during both read and write access. The high write current density stresses the tunnel barrier and degrades its reliability during the write operation of the STT-MRAM cell [10]. The reliability of the STT-MRAM technology can be improved if the write current does not flow through the tunnel barrier
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