RAM Technology Research Articles

Ouroboros Wear Leveling for NVRAM Using Hierarchical Block Migration

Emerging nonvolatile RAM (NVRAM) technologies have a limit on the number of writes that can be made to any cell, similar to the erasure limits in NAND Flash. This motivates the need for wear leveling techniques to distribute the writes evenly among the cells. Unlike NAND Flash, cells in NVRAM can be rewritten without the need for erasing the entire containing block, avoiding the issues of space reclamation and garbage collection, motivating alternate approaches to the problem. In this article, we propose a hierarchical wear-leveling model called Ouroboros wear leveling. Ouroboros uses a two-level strategy whereby frequent low-cost intraregion wear leveling at small granularity is combined with interregion wear leveling at a larger time interval and granularity. Ouroboros is a hybrid migration scheme that exploits correct demand predictions in making better wear-leveling decisions while using randomization to avoid wear-leveling attacks by deterministic access patterns. We also propose a way to optimize wear-leveling parameter settings to meet a target smoothness level under limited time and space overhead constraints for different memory architectures and trace characteristics. Several experiments are performed on synthetically generated memory traces with special characteristics, two block-level storage traces, and two memory-line-level memory traces. The results show that Ouroboros wear leveling can distribute writes smoothly across the whole NVRAM with no more than 0.2% space overhead and 0.52% time overhead for a 512GB memory.

An Efficient Heterogeneous Memristive xnor for In-Memory Computing

Resistive RAM (RRAM) technologies are gaining importance due to their appealing characteristics, which include non-volatility, small form factor, low power consumption, and ability to perform logic operations in memory. These characteristics make RRAM highly suited for Internet of Things devices and similarly resource-constrained systems. This paper proposes a novel memristor-based xnor gate that enables the execution of xnor/xor function in the memristive crossbar memory. The proposed two-input xnor gate requires two steps to perform the xnor function. The design of the circuit utilizes bipolar and unipolar memristors and permits cascading by only adding an extra step and one computing memristor. To the best of our knowledge, this is the first native stateful xnor logic implementation. Spice simulations have been used to verify the functionality of the proposed circuit. This includes benchmarking the proposed design against the state-of-the-art stateful memristor-based logic circuits. The results for implementing three-input xor using the proposed circuit demonstrate efficient performance in terms of energy, latency, and area. The gate shows 56% saving in energy, 54% less number of steps (latency), and 50% less number of computing MR (area) compared with the state-of-the-art stateful xor/xnor implementations.

The Memristive Boltzmann Machines

The Boltzmann machine is a massively parallel computational model capable of solving a broad class of combinatorial optimization problems. In recent years, it has successfully been applied to training deep machine learning models on massive datasets. High-performance implementations of the Boltzmann machine using GPUs, MPI-based high-performance computing clusters, and field-programmable gate arrays have been proposed in the literature. Regrettably, the required all-to-all communication among the processing units limits the performance of these efforts. The proposed memristive Boltzmann machine is a massively parallel, memory-centric hardware accelerator based on recently developed resistive RAM (RRAM) technology. The proposed accelerator exploits the electrical properties of RRAM to realize in situ, fine-grained parallel computation within memory arrays, thereby eliminating the need for exchanging data between the memory cells and the computational units.

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

The breakdown of Dennard scaling prevents us from powering all transistors simultaneously, leaving a large fraction of dark silicon. This crisis has led to innovative work on power-efficient core and memory architecture designs. However, the research for addressing dark silicon challenges with network-on-chip (NoC), which is a major contributor to the total chip power consumption, is largely unexplored. In this paper, we comprehensively examine the network power consumers and the drawbacks of the conventional power-gating techniques. To overcome the dark silicon issue from the NoC's perspective, we propose DimNoC, a dim silicon scheme, which leverages recent drowsy SRAM design and spin-transfer torque RAM (STT-RAM) technology to replace pure SRAM-based NoC buffers. In particular, we propose two novel hybrid buffer architectures: 1) a hierarchical buffer architecture, which divides the input buffers into a set of levels with different power states and 2) a banked buffer architecture, which organizes the drowsy SRAM and the STT-RAM in different banks, and accesses them in an interleaved fashion to hide the long write latency of STT-RAM. In addition, our hybrid buffer design enables NoC data retention mechanism by storing packets in drowsy SRAM and nonvolatile STT-RAM in a lossless manner. Combined with flow control schemes, the NoC data retention mechanism can improve network performance and power simultaneously. Our experiments over real workloads show that DimNoC can achieve 30.9% network energy saving, 20.3% energy-delay product reduction, and 7.6% router area reduction compared with pure SRAM-based NoC design.

Frequency Based Energy Efficient Motley RAM Design on 40nm FPGA Technology

This paper incorporates the most efficient layout of the RAM in terms of the power consumption. Various RAM styles have been thoroughly analyzed. Frequency analysis has been done for RAM on 40nm FPGA. The main focus has been on studying the various power consumption parameters (total power, I/O power, signal power and the clock power) at different frequencies for the different layouts. We focus highly to find out the optimum conditions at which the RAM behaves the best. Frequency variations and its effect on the RAM technologies is basically the main point of concern. Lesser the power consumption, more efficiently would the circuit behave because the improvidence in terms of power consumption is reduced. The analysis has been done using the Verilog VHDL language and XILINX 12.1. We lead to a conclusion that the distributed style is the most preferred one and that too at a lower value of frequency. This research would open up many avenues in the field of electronics and communication regarding the design of various energy efficient RAM designs on the FPGA.

Once More Unto the Breach

Summary: Recently, Susan Cohen composed an article entitled, “Interpretative Uses and Abuses of the Beni Hasan Tomb Painting” (JNES 74–1 (2015):19–38), in which she re-evaluated scholars’ claims derived from the famous depiction of Asiatic foreigners arriving in the Oryx Nome. Cohen persuasively argued that, although this depiction can be informative, we should be wary of constructing elaborate conclusions as it appears that there is an inherent temptation to over-emphasize this scene’s importance in reconstructing pharaonic history. In a similar vein, academics have misconstrued the siege practices involving battering ram technology and the purpose of a glacis from three tombs at Beni Hasan (Baqt (BH15), Khety (BH17), and Amenemhat (BH2)). Generally, Egyptologists and ancient Near Eastern scholars have long applied the Beni Hasan siege scenes as an example of the first Egyptian representational evidence of the battering ram. However, there have been virtually no attempts to place the Beni Hasan siege device into its Egyptian and ancient Near Eastern context. A comprehensive examination of textual and archaeological information regarding battering rams will be conducted herein to re-evaluate the siege scenes of Beni Hasan. From this, we can carefully assess if the scenes suggest the proliferation of battering-ram technology used by the pharaonic military. After discussing the Beni Hasan battering ram, we will also re-examine the sloped sides of the fortress representations misidentified by many as a “glacis” and deduced that this architecture feature was specifically designed to counter battering ram deployment.

Investigation of Cycle-to-Cycle Variability in HfO2-Based OxRAM

This letter studies the intrinsic variability in oxide-based resistive RAM technology, highlighting the presence of a short range ( $\approx 40$ ) correlation of resistances among cycles (for both low resistance state and high resistance state). Experimental results demonstrate the existence of a resistance correlation, and an analytical model is proposed in order to explain the findings. The presence of the correlation seems to indicate that the conductive filament, which is believed to be the basis of resistive RAM behavior, keeps for a limited number of cycling operations a memory of its morphology. The extension of this correlation depends on the programming conditions.

DESIGN OF A 4-BIT NON-VOLATILE SRAM USING MAGNETIC TUNNEL JUNCTION

In this paper, we propose a non-volatile SRAM, which presents simultaneously low power dissipation and high speed. This SRAM is based on MRAM (Magnetic RAM technology on standard CMOS. In this non-volatile SRAM design, we use Magnetic Tunnel Junctions (MTJ) as storage element. A 4-bit SRAM cell is designed and its read-write operations are described. Sense Amplifier is used in the read operation model. Two Write-Enable transistors and two inverters are used in the write operation model. The 4-bit SRAM cell has been implemented using Tanner tool. The operation of the SRAM cell is clearly understood from the output waveforms obtained after implementation. The structure and working of Magnetic Tunnel Junction is studied. The design of a Non-Volatile SRAM using Magnetic Tunnel Junction is proposed.

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories

The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer torque magnetic RAM (STT-MRAM) technology shows comparable performance in terms of speed and power consumption and much better performance in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent nonvolatility, which allows the definition of new instant-on/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process. Through simulations, first we demonstrate that STT-MRAM is a candidate for the memory part of embedded systems, and second we implement a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high-level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on power consumption is finally evaluated with regard to various shutdown and restart behaviors.

Benchmarking in-memory database

We have witnessed exciting development of RAM technology in the past decade. The memory size grows rapidly and the price continues to decrease, so that it is feasible to deploy large amounts of RAM in a computer system. Several companies and research institutions have devoted a lot of resources to develop in-memory databases (IMDB) that implement queries after loading data into (virtual) memory in advance. The bloom of various in-memory databases pursues us to test and evaluate their performance objectively and fairly. Although the existing database benchmarks like Wisconsin benchmark and TPC-X series have achieved great success, they cannot suit for in-memory databases due to the lack of consideration of unique characteristics of an IMDB. In this study, we propose MemTest, a novel benchmark that concerns some major characteristics of an in-memory database. This benchmark constructs particular metrics, which cover processing time, compression ratio, minimal memory space and column strength of an in-memory database. We design a data model based on inter-bank transaction applications, and a data generator to support uniform and skew data distributions. The MemTest workload includes a set of queries and transactions against the metrics and data model. Finally, we illustrate the efficacy of MemTest through the implementations on two different in-memory databases.

Hexagonal Ferrite Fibres and Nanofibres

Hexagonal ferrites, or hexaferrites, are hugely important materials commercially and technologically, with common applications as permanent magnets, magnetic recording and data storage media, components in electrical devices operating at wireless frequencies, and as GHz electromagnetic wave absorbers for EMC, RAM and stealth technologies. Hexaferrites are all ferrimagnetic materials, and their magnetic properties are intrinsically linked to their crystalline structures, all having a strong magnetocrystalline anisotropy; that is the induced magnetisation has a preferred orientation within the crystal structure. They can be divided into two main groups: those with an easy axis of magnetisation (known as uniaxial), the hard hexaferrites, and those with an easy plane (or cone) of magnetisation (known as ferroxplana or hexaplana), soft ferrites. The common hexaferrite members are:M-type ferrites, such as BaFe12O19and SrFe12O19Z-type ferrites (Ba3Me2Fe24O41)Y-type ferrites (Ba2Me2Fe12O22)W-type ferrites (BaMe2Fe16O27)X-type ferrites (Ba2Me2Fe28O46)U-type ferrites (Ba4Me2Fe36O60)where Me = a small 2+ion such as cobalt, nickel or zinc, and Ba can be fully substituted by Sr. Generally, the M ferrites are hard, the Y, Z and U ferrites are soft, and the W and X ferrites can very between these two extremes, but all have large magnetisation (M) values.There is currently increasing interest in composite materials containing hexaferrite fibres. It had been predicted that properties such as thermal and electrical conductivity, and magnetic, electrical and optical behaviour will be enhanced in material in fibrous form. This is because a continuous fine fibre can be considered as effectively one-dimensional, and it does not behave as a homogeneously distributed solid. Although the intrinsic magnetisation of the material is unaffected, the effective magnetisation of an aligned fibre sample should be greater when a field is applied parallel with fibre alignment compared to when applied perpendicularly to fibre alignment. This feature was first demonstrated by the author for aligned hexaferrite fibres in 2006. This chapter will deal with progress in the manufacture and properties of hexaferrite fibres, from the first syntheses of BaM, SrM,Co2Y,Co2Z, Co2W, Co2X and Co2U micron-scale fibres by the author 12-15 years ago, to recent developments in M ferrite hollow fibres and nanofibres, and hexaferrite-coated CNTs (carbon nanotubes).The relative properties of all reported hexaferrite fibres are compared and summarised at the end of this chapter.

Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing

Power dissipation and memory bandwidth are significant performance bottlenecks in virtually all computer systems. Associative computing with ternary content addressable memory (TCAM) holds the potential to address both problems in a wide range of data intensive workloads. Power dissipation is reduced by eliminating instruction processing and data movement overheads present in a purely RAM-based system. Bandwidth demand is lowered by processing data directly on the TCAM chip, thereby decreasing off-chip traffic. Unfortunately, existing SRAM-based TCAM cells are more than 90 times larger than a DRAM cell at the same technology node, which limits the capacity of commercially available TCAMs to a few megabytes. This article examines the integration of gigascale TCAM systems based on resistive memories within a general-purpose computing platform. TCAM density is improved by novel, resistive memory cells that exploit phase change and spin-toque transfer magnetoresistive RAM technologies. TCAM chips are organized into a DDR3-compatible DIMM and are accessed through a software library with zero modifications to the processor or the motherboard. The proposed TCAM systems achieve average speedups of 3 to 4.5 times and average energy reductions of 5 to 8 times as compared to a conventional RAM-based system.

Design of Hybrid Second-Level Caches

In recent years, embedded dynamic random-access memory (eDRAM) technology has been implemented in last-level caches due to its low leakage energy consumption and high density. However, the fact that eDRAM presents slower access time than static RAM (SRAM) technology has prevented its inclusion in higher levels of the cache hierarchy. This paper proposes to mingle SRAM and eDRAM banks within the data array of second-level (L2) caches. The main goal is to achieve the best trade-off among performance, energy, and area. To this end, two main directions have been followed. First, this paper explores the optimal percentage of banks for each technology. Second, the cache controller is redesigned to deal with performance and energy. Performance is addressed by keeping the most likely accessed blocks in fast SRAM banks. In addition, energy savings are further enhanced by avoiding unnecessary destructive reads of eDRAM blocks. Experimental results show that, compared to a conventional SRAM L2 cache, a hybrid approach requiring similar or even lower area speedups the performance on average by 5.9 percent, while the total energy savings are by 32 percent. For a 45 nm technology node, the energy-delay-area product confirms that a hybrid cache is a better design than the conventional SRAM cache regardless of the number of eDRAM banks, and also better than a conventional eDRAM cache when the number of SRAM banks is an eighth of the total number of cache banks.

Preparation of an Energetic‐Energetic Cocrystal using Resonant Acoustic Mixing

AbstractResonant acoustic mixing (RAM) was applied to the preparation of an energetic‐energetic cocrystal comprised of CL‐20 and HMX in a 2 : 1 mol ratio. We have prepared the cocrystal using the RAM technology in a resource‐efficient manner providing near quantitative yield. The cocrystalline product from the RAM preparation is consistent with the product from solution crystallization.

ChemInform Abstract: Hexagonal Ferrites: A Review of the Synthesis, Properties and Applications of Hexaferrite Ceramics

AbstractReview: 560 refs.

IBM zEnterprise 196 microprocessor and cache subsystem

The IBM zEnterprise® 196 (z196) system, announced in the second quarter of 2010, is the latest generation of the IBM System z® mainframe. The system is designed with a new microprocessor and memory subsystems, which distinguishes it from its z10® predecessor. The system has up to 40% improvement in performance for traditional z/OS® workloads and carries up to 60% more capacity when compared with its z10 predecessor. The memory subsystem has four levels of cache hierarchy (L1 through L4) and constructs the L3 and L4 caches with embedded DRAM silicon technology, which achieves approximately three times the cache density over traditional static RAM technology. The microprocessor has 50% more decode and dispatch bandwidth when compared with the z10 microprocessor, as well as an out-of-order design that can issue and execute up to five instructions every single cycle. The microprocessor has an advanced branch prediction structure and employs enhanced store queue management algorithms. At the date of product announcement, the microprocessor was the fastest complex-instruction-set computing processor in the industry, running at a sustained 5.2 GHz, executing approximately 1,100 instructions, 220 of which are cracked into reduced-instruction-set computing-type operations, to achieve large performance gains in legacy online transaction processing and compute-intensive workloads.

Crucible Fluxing with Hycast™ RAM- Effect on Metal Quality and Operational Cost

Hycast TM RAM, hereafter called RAM, is a crucible fluxing technology for removal of alkaline elements (Na, Ca, and Li), as well as carbides, oxides and cryolite, from aluminium pot-room metal without the use of chlorine. AlF3 powder is injected into the liquid metal (below the metal surface) by the use of a specially designed rotor system and argon as a carrier gas. The fluxing system can be adapted to different crucible transport/tapping system, and is proven for crucible sizes from 2 to 9 tons. Since surface active elements like Sodium are removed before the metal enters into the furnace, the metal oxidation during pouring and furnace treatment is significantly reduced. Pretreatment will also reduce the carbide level in the metal, and by this improve the overall metal quality, and prevent clogging/deposits in furnaces, degassers, ceramic foam filters etc. This paper describes the principles of the RAM technology, effect on metal quality and documented operational benefits in a primary casthouse. Also environmental issues are discussed.

Challenges toward gigabit-scale spin-transfer torque random access memory and beyond for normally off, green information technology infrastructure (Invited)

If spin-transfer torque RAM (SPRAM) technology is used as a true nonvolatile RAM, it will be able to provide normally “off” and instant “on” functions. This would drastically reduce the power consumption of information technology (IT) equipment and its infrastructure while preserving high performance, thus leading to a green IT infrastructure. This paper describes the design issues and solutions for creating a Gb-scale SPRAM; scaling in memory cell current (∝F, F: feature size) and the tunneling magnetoresistive (TMR) device’s write current (∝F2), the maximum voltage applicable to a TMR device (TMR ratio and resistance area product are considered); and the thermal stability of the TMR device (depending on the operation mode and density). Moreover, the cell and array configurations and an indispensable disruptive reading operation are shown for 4F2DDRx compatible operations. SPRAM can cover a system composed of a DRAM region. Finally, the potential of a multibit memory structure that covers the area of a not-and flash memory is discussed.

Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing

Nonvolatile embedded memories may open the door to new computing paradigms based on "normally-off and instant-on" operation. This article covers recent trends of spin-transfer-torque RAM technology, an emerging class of nonvolatile memory, and discusses its impact on the different layers of computer system hierarchy.

Performance of two-stage shared fiber delay line optical packet switch under bursty traffic

Packet contention is a major issue in an optical packet switching network. It is not a trivial task to resolve contention due to lack of optical RAM technology. This article proposes a two-stage shared fiber delay line (FDL) optical packet switch for contention resolution. In this article, shared FDLs are used to buffer optical packets, in which a pool of buffer memory is shared among all switch output ports. Most of the existing optical buffering schemes are output-based which require a huge number of FDLs as well as a larger switch size that incur extra implementation cost. However, a shared buffering approach is considered in this article in order to reduce implementation cost. In this article, FDLs are implemented in two stages using an extremely simple auxiliary switch. The proposed switch architecture leads to more efficient use of buffer space. The superiority of the proposed switch architecture has been established by means of extensive simulations. The performance of the proposed switch is investigated under bursty traffic. Simulation result shows that the proposed switch can achieve satisfactory performance at the price of a reasonable amount of FDLs. Moreover, the significance of the proposed switch is confirmed by simulation.