Block RAMs Research Articles

Method for synthesis of models for assessing the state of ram memory of operators of human-machine systems based on fuzzy decision making logic

The purpose of the research is to develop a method for synthesizing models for assessing the state of RAM of operators of human-machine systems, the use of which in the decisive rules for predicting and diagnosing the states of RAM and its blocks ensures an increase in the quality of decisions made.Methods. To monitor the state of various RAM blocks, the following set of techniques was selected: searching for a signal in noise; "identification"; full reproduction; identification of missing digits; Memory. To select an adequate mathematical research apparatus, an exploratory analysis of the structure of the processed data was carried out, during which it was found that the selected classes of RAM states are of a fuzzy nature with uncertain boundaries of their intersections. Taking into account the peculiarities of the processed data, the selected methodology was modified by developing a new method for fuzzy assessment of the state of RAM based on the characteristics of its properties in combination with informative features characterizing the ergonomics of the workplace, the environmental component and individual risk factors.Results. In the course of the research, a model was synthesized for predicting the appearance and development of dysfunctions of RAM in operators of information-rich systems, characterized by the use of indicators characterizing the state of RAM blocks as predictors, which allows one to obtain confidence in the correct decision-making of no worse than 0,85.Conclusion. In the course of the studies, it was shown that in order to improve the quality indicators of forecasting and diagnosing the states of RAM and its blocks, when synthesizing the corresponding decision rules, indicators characterizing the state of RAM blocks, energy imbalance of BAP, ergonomic and individual risk factors should be taken into account. With this approach, in forecasting problems, confidence in the correct decision-making is achieved at least 0,85. In the tasks of diagnosing the early stages of RAM disorders among operators of information-rich systems, confidence in correct decision-making exceeds 0,95.

The method and fuzzy models for evaluating the functional states of RAM

The purpose of the research is to improve the quality of assessment of functional states of working memory by developing a method for synthesizing fuzzy decision rules.Methods. To monitor the state of various RAM blocks, a set of techniques was selected: reaction time assessment; searching for a signal in noise; "identification"; full reproduction; identification of missing digits; Memory. To synthesize decision rules, additional methods were used to assess such properties of attention as switchability, concentration and stability, for the implementation of which a device for monitoring the properties of the attention and memory function was used. To select an adequate mathematical research apparatus, an exploratory analysis of the structure of the processed data was carried out, according to which it was established that the selected classes of RAM states are of a fuzzy nature with uncertain boundaries of their intersections. Taking this into account, the methodology for the synthesis of hybrid fuzzy decision rules was chosen as a mathematical research tool, which was modified by developing a new method for fuzzy assessment of the functional state of RAM based on the characteristics of its properties.Results. In the course of the research, models were synthesized to assess such characteristics of the functional state as levels of fatigue, psycho-emotional stress and the functional state of RAM using the full reproduction method. The resulting models can be used to synthesize decision rules for forecasting, early and differential diagnostics of the functional state, assessing the quality of work of the operator of human-machine systems and the health status of RAM.Conclusion. The paper proposes a method for synthesizing fuzzy decision rules for assessing the functional state of RAM based on the characteristics of its properties using techniques obtained from the results of microstructural analysis. Fuzzy decision rules were obtained for assessing the level of fatigue, psycho-emotional stress and the functional state of RAM using the full reproduction method. During expert assessment and mathematical modeling, it was shown that confidence in the correct assessment of the level of functional state exceeds 0,95.

A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection

In today’s increasingly complex traffic environment, pedestrian detection has become increasingly important. The Histogram of Oriented Gradients (HOG) algorithm has been proven to be highly efficient in pedestrian detection. This paper proposes a low-resource consumption, high-speed hardware implementation for HOG algorithm. In the case of a slight sacrifice in accuracy, it increases computational speed and reduces resource consumption. Experimental results demonstrate that the implementation achieves a speed of 0.933 pixels per clock cycle and consumes 4117 look-up tables and 4.5 Kbits of block RAMs while its accuracy decreases by 1.2% on the INRIA dataset and by 0.11% on the MIT dataset.

CIPO: Efficient, lightweight and programmable packet scheduling

With the rapid development of network devices and increasingly high CPU workloads, packet scheduling will have to be offloaded to hardware. Programmable packet scheduling allows scheduling algorithms to be programmed into network devices without modifying the hardware. It not only retains the flexibility of software but also the scalability of hardware. In existing primitives, the most expressive Push-In-ExtractOut (PIEO) is prohibitively expensive to implement due to its complexity. While its variant, Push-In-Pick-Out (PIPO), offers some improvements, it suffers from insufficient scalability. In this paper, we propose the Classify-In-Push-Out (CIPO) primitive. The core idea of CIPO is to track the rank and predicate of recent packets through a sliding window, filter and classify packets using a prediction-based two-dimensional classification algorithm and a finite number of First-In-First-Out (FIFO) queues. Through theoretical analysis and evaluation with a range of real workloads, CIPO proves that it has a scheduling performance similar to the most expressive scheduling primitive. Importantly, CIPO requires fewer hardware resources while still providing sufficient expressiveness. Primitive on FPGA show that the CIPO-based scheduler achieves an average of 1.24× higher throughput than the PIEO-based scheduler but uses only an average of 26.2% of look-up tables (LUTs) and 12.2% of the block RAM of the latter.

Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function.

The implementation of neural networks (NNs) on edge devices enables local processing of wireless data, but faces challenges such as high computational complexity and memory requirements when deep neural networks (DNNs) are used. Shallow neural networks customized for specific problems are more efficient, requiring fewer resources and resulting in a lower latency solution. An additional benefit of the smaller network size is that it is suitable for real-time processing on edge devices. The main concern with shallow neural networks is their accuracy performance compared to DNNs. In this paper, we demonstrate that a customized adaptive activation function (AAF) can meet the accuracy of a DNN. We designed an efficient FPGA implementation for a customized segmented spline curve neural network (SSCNN) structure to replace the traditional fixed activation function with an AAF. We compared our SSCNN with different neural network structures such as a real-valued time-delay neural network (RVTDNN), an augmented real-valued time-delay neural network (ARVTDNN), and deep neural networks with different parameters. Our proposed SSCNN implementation uses 40% fewer hardware resources and no block RAMs compared to the DNN with similar accuracy. We experimentally validated this computationally efficient and memory-saving FPGA implementation of the SSCNN for digital predistortion of radio-frequency (RF) power amplifiers using the AMD/Xilinx RFSoC ZCU111. The implemented solution uses less than 3% of the available resources. The solution also enables an increase of the clock frequency to 221.12 MHz, allowing the transmission of wide bandwidth signals.

Partitioned 2D Set-Pruning Segment Trees with Compressed Buckets for Multi-Dimensional Packet Classification

Abstract Multi-dimensional packet classification is one of the most important functions to support various services in next generation routers. Both the memory-efficient data structure to support larger rule tables and the hardware architecture to achieve a higher throughput are desired. In this paper, we propose a parallel and pipelined architecture called Set-Pruning Segment Trees with Buckets (SPSTwB) for multi-dimensional packet classification. SPSTwB significantly reduces rule duplication based on a novel partitioning scheme and an efficient bucket merging scheme. The key feature of our proposed architecture is that memory consumption is reduced significantly regardless of the characteristics of various rule tables. In addition, the logic complexity of each pipeline stage is simplified by not storing rule IDs and priorities and thus it can run at a high clock rate. The proposed scheme needs less than 20 bytes per rule for various 100 K rule tables generated by ClassBench. In addition, the proposed scheme supports fast incremental rule update. The proposed pipelined architecture can achieve a throughput of 134 Gbps from the implementation on Xilinx Virtex-7 FPGA device with dual-ported Block RAM.

An Advanced Method of Testing Memories Using a Vedic March Algorithm

Nowadays, as the technology grows the size of the chip decreases, and RAM testing becomes more critical whose input and output ports are not controlled directly through the input or output pins of an IC. Because of the absence of controllability of RAM at the input or observing the output ports, testing is a tougher and more challenging effort. Multiple RAM testing is the main theme of the paper. Existing ways of testing RAMs for testing address data in random ways and missed corner cases, in the proposed system we come up with the new idea of testing RAMs using VMA (a Vedic March Algorithm). In the existing system using VMA tested a single RAM and by using a similar technique added multiple blocks of RAM and tested using VMA, for input generation of bits we used a BIST controller. we proved the 60% efficiency of the output is more comparable to the existing designs which standardize to improve march algorithms and observed a 10% decrease in the area compared to the existing systems. The proposed system uses a built-in self-test for generating a randomized cyclic address with the Vedic march algorithm which improves the level of testing of RAMs by randomizing reads and write flows to check and achieve higher efficiency. Simulation results are carried out by Synopsys VCS using Verilog HDL of reads and writes of different memories using March techniques.

FPGA based modified multi-repeat distribution matcher for probabilistic amplitude shaping

The technique of probabilistic amplitude modulation, based on distribution matching, has garnered considerable attention in recent years as a means to enhance spectral efficiency and diminish the constellation energy of coded modulation. This paper introduces the implementation of Probabilistic Amplitude Modulation (PAS) using a Modified Multi-Repeat Distribution Matcher (MMRDM) on a Field Programmable Gate Array (FPGA). The Modified Multiple Repetition Distribution Matcher (MMRDM) is integrated into a 2×2 Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system, realized through the Xilinx System Generator (XSG). Simple Zero-Forced and Minimum Mean Squared Error (MMSE) equalizers are applied to the receiver for signal detection across the MIMO channel. The system incorporates enhanced security through chaos-based scrambling with 16 and 64 Quadrature Amplitude Modulation (QAM). VHDL code files for this system are generated for the Xilinx Kintex-7 (xc7k325t-3fbg676) for hardware implementation. Performance evaluation includes an assessment of required storage capacity, complexity, and bit error rate (BER). Using Vivado 2017.4, the system is successfully routed with resource utilization, for example, 0.67% Block RAM (BRAM), 68.6% Look-Up Tables (LUT), 83% DSP 48s, and 1.5% registers for 64-QAM uniform modulation. Similarly, for 64-QAM 10 level (shaper output 60 bit) shaped modulation, the resource utilization is 0.67% BRAM, 68.8% LUT, 83% DSP 48s, and 1.6% registers on the specified device. Simulation results demonstrate an improvement in the net shaping gain of approximately (2-4 dB) at 1×10^(-4) for different equalizer cases compared to uniform QAM, along with a notable reduction in required storage capacity and computational complexity.

Design and Implementation of a Low-Complexity Multi-h CPM Receiver with Linear Phase Approximation Synchronization Algorithm.

Multi-h continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-h continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-h CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-h CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method.

On the RTL Implementation of FINN Matrix Vector Unit

Field-programmable gate array (FPGA)–based accelerators are becoming increasingly popular for deep neural network (DNN) inference due to their ability to scale performance with increasing degrees of specialization with dataflow architectures or custom data type precision. In order to reduce the barrier for software engineers and data scientists to adopt FPGAs, C++- and OpenCL-based design entries with high-level synthesis (HLS) have been introduced. They provide higher abstraction compared with register-transfer level (RTL)–based design. HLS offers faster development time, better maintainability, and more flexibility in code exploration when evaluating several options for multi-dimension tensors, convolutional layers, or different degrees of parallelism. For this reason, HLS has been adopted by DNN accelerator generation frameworks such as FINN and hls4ml. In this article, we present an alternative backend library for FINN, leveraging RTL. We investigate and evaluate, across a spectrum of design dimensions, the pros and cons of an RTL-based implementation versus the original HLS variant. We show that for smaller design parameters, RTL produces significantly smaller circuits as compared with HLS. For larger circuits, however, the look-up table (LUT) count of RTL-based design is slightly higher, up to around 15%. On the other hand, HLS consistently requires more flip-flops (FFs; with an orders-of-magnitude difference for smaller designs) and block RAMs (BRAMs; 2× more). This also impacts the critical path delay, with RTL producing significantly faster circuits, up to around 80%. RTL also benefits from at least a 10× reduction in synthesis time. Finally, the results were validated in practice using two real-world use cases, one of a multi-layer perceptron (MLP) used in network intrusion detection and the other a convolution network called ResNet, used in image recognition. Overall, since HLS frameworks code-generate the hardware design, the benefits of the ease in the design entry is less important. As such, the gained benefits in synthesis time together with some design-dependent resource benefits make the RTL abstraction an attractive alternative.

A Low-Delay Dynamic Range Compression and Contrast Enhancement Algorithm Based on an Uncooled Infrared Sensor with Local Optimal Contrast

Real-time compression of images with a high dynamic range into those with a low dynamic range while preserving the maximum amount of detail is still a critical technology in infrared image processing. We propose a dynamic range compression and enhancement algorithm for infrared images with local optimal contrast (DRCE-LOC). The algorithm has four steps. The first involves blocking the original image to determine the optimal stretching coefficient by using the information of the local block. In the second, the algorithm combines the original image with a low-pass filter to create the background and detailed layers, compressing the background layer with a dynamic range of adaptive gain, and enhancing the detailed layer for the visual characteristics of the human eye. Third, the original image was used as input, the compressed background layer was used as a brightness-guided image, and the local optimal stretching coefficient was used for dynamic range compression. Fourth, an 8-bit image was created (from typical 14-bit input) by merging the enhanced details and the compressed background. Implemented on FPGA, it used 2.2554 Mb of Block RAM, five dividers, and a root calculator with a total image delay of 0.018 s. The study analyzed mainstream algorithms in various scenarios (rich scenes, small targets, and indoor scenes), confirming the proposed algorithm’s superiority in real-time processing, resource utilization, preservation of the image’s details, and visual effects.

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

Efficient On-Chip Learning of Multi-Layer Perceptron Based on Neuron Multiplexing Method

An efficient on-chip learning method based on neuron multiplexing is proposed in this paper to address the limitations of traditional on-chip learning methods, including low resource utilization and non-tunable parallelism. The proposed method utilizes a configurable neuron calculation unit (NCU) to calculate neural networks in different degrees of parallelism through multiplexing NCUs at different levels, and resource utilization can be increased by reducing the number of NCUs since the resource consumption is predominantly determined by the number of NCUs and the data bit-width, which are decoupled from the specific topology. To better support the proposed method and minimize RAM block usage, a weight segmentation and recombination method is introduced, accompanied by a detailed explanation of the access order. Moreover, a performance model is developed to facilitate parameter selection process. Experimental results conducted on an FPGA development board demonstrate that the proposed method has lower resource consumption, higher resource utilization, and greater generality compared to other methods.

Parameterized SDRAM-based content-addressable memory on field programmable gate array

Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besides, the collision ratio is high in FPGA-based CAMs, leading to data loss and failure to produce accurate addresses. Synchronous dynamic random-access memory (SDRAM)-based CAMs, benefiting from the features of high density and low price of SDRAM, solve the limitations of FPGA’s on-chip resources. This paper proposes a data collision CAM hardware implementation using modern FPGA’s off-chip SDRAM for data storage. The hardware architecture is customized for massive lookup tables and resource-saving. Furthermore, the architecture is parameterized, which is better for integration. The synthesis results and comparisons show significant advancement compared to other FPGA-based CAM implementations by total reduction of on-chip RAM. The novel architecture shows remarkable improvement in the memory depth and width with the capacity of 128 Mbyte lookup table.

CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration

Block random access memories (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using logic blocks and digital signal processing slices. We propose modifying BRAMs to convert them to CoMeFa ( Co mpute-in- Me mory Blocks for F PG A s) random access memories (RAMs). These RAMs provide highly parallel compute-in-memory by combining computation and storage capabilities in one block. CoMeFa RAMs utilize the true dual-port nature of FPGA BRAMs and contain multiple configurable single-bit bit-serial processing elements. CoMeFa RAMs can be used to compute with any precision, which is extremely important for applications like deep learning (DL). Adding CoMeFa RAMs to FPGAs significantly increases their compute density while also reducing data movement. We explore and propose two architectures of these RAMs: CoMeFa-D (optimized for delay) and CoMeFa-A (optimized for area). Compared to existing proposals, CoMeFa RAMs do not require changing the underlying static RAM technology like simultaneously activating multiple wordlines on the same port, and are practical to implement. CoMeFa RAMs are especially suitable for parallel and compute-intensive applications like DL, but these versatile blocks find applications in diverse applications like signal processing and databases, among others. By augmenting an Intel Arria 10–like FPGA with CoMeFa-D (CoMeFa-A) RAMs at the cost of 3.8% (1.2%) area, and with algorithmic improvements and efficient mapping, we observe a geomean speedup of 2.55× (1.85×) across microbenchmarks from various applications and a geomean speedup of up to 2.5× across multiple deep neural networks. Replacing all or some BRAMs with CoMeFa RAMs in FPGAs can make them better accelerators of DL workloads.

Measurements of radiation effects in an antifuse FPGA

This paper presents the irradiation and the measurement analysis for a commercial antifuse Field Programmable Gate Array (FPGA) from Microsemi’s Axcelerator family, part number AX250. Following proton and X-ray beam irradiation, at very high dose rate above 1krad/s, the total ionizing dose (TID) first effects were visible around 260 krad (SiO 2), and this threshold value increases at lower radiation dose rates. We expect for most space and accelerator applications that this value will be at least several Mrads, or even that the FPGA might never reach this threshold. At very high radiation dose rates, TID-induced leakage currents were observed in the device. FPGA data were recorded continuously for more than 100 h after each irradiation with a fully operating FPGA. Quantitatively, the room-temperature annealing of the radiation-induced defects leads to a fast decrease of the device leakage current by a factor of 7 in the first 100 h after irradiation. The last measurements done after three months place the currents to within 30% to 70 % relative to the before-irradiation values in case of two tested FPGA. Several firmware configurations were used to test different logic resources and to measure single event upsets (SEUs). An upper limit of SEU logic cross-section was found to be (2.56 ± 0.51) ⋅ 10−13 cm 2/FPGA for dose rates around 1krad/s. SEU cross-section values for RAM blocks have on average a value of (3.72 ± 0.8) ⋅ 10−14 cm 2/bit. The complete list of results is given and the effects are extrapolated to a high-energy physics experiment environment — LHCb RICH at CERN.

Object Detection Using Adaptive Block Partition and RCNN Algorithm

Advancements in image and video processing are growing over the years for industrial robots, autonomous vehicles, cryptography, surveillance, medical imaging and computer-human interaction applications. One of the major challenges in real-time image and video processing is the execution of complex functions and high computational tasks. To overcome this issue, a hardware acceleration of different filter algorithms for both image and video processing is implemented on Xilinx Zynq®-7000 System on-Chip (SoC) device consists of Dual-core Cortex™-A9 processors which provides computing ability to perform with the help of software libraries using Vivado® High-Level Synthesis (HLS). The acceleration of object detection algorithms include Sobel-Feldman filter, posterize and threshold filter algorithms implemented with 1920 x 1080 image resolutions for real-time object detection. The implementation results exhibit effective resource utilization such as 45.6% of logic cells, 51% of Look-up tables (LUTs), 29.47% of Flipflops, 15% of Block RAMs and 23.63% of DSP slices under 100 MHz frequency on comparing with previous works. There are a few reasons why tracking is preferable over detecting objects in each frame. Tracking facilitates in identifying the identity of various items across frames when there are several objects. Object detection may fail in some instances, but tracking may still be achievable which takes into account the location and appearance of the object in the previous frame. The key hurdles in real-time image and video processing applications are object tracking and motion detection. Some tracking algorithms are extremely fast because they perform a local search rather than a global search. Tracking algorithms such as meanshift, Regional Neural Network probabilistic data association, particle filter, nearest neighbor, Kalman filter and interactive multiple model (IMM) are available to estimate and predict the state of a system.

Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism

Molecular docking (MD) is one of the core steps in the expensive and time-consuming process of drug design, which is basically an optimization problem based on scoring functions. AutoDock series MD software is widely accepted by academia and industry, among which AutoDock Vina (Vina) is the latest and most popular version due to its accuracy and relatively high speed. However, contrast to its prior version, i.e., AutoDock4, hardware acceleration approaches of Vina are rarely reported. In this article, we propose Vina-field-programmable gate array (FPGA), a hardware-accelerated Vina implementation with FPGA that exploits the low-level parallelism. First, the fixed-point quantization is analyzed and realized to accelerate the MD algorithm with a better energy efficiency in hardware. To boost the performance of the module-level computation, multiple in- module hardware pipelines have been designed and implemented. Besides, a strategy for fast accessing to block RAM (BRAM) is implemented by utilizing the layout of data, which brings four times memory access speed to the intermolecular and intramolecular energy computing modules. Under the same 140 ligand–receptor benchmarks, Vina-FPGA performs up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.9\times $ </tex-math></inline-formula> (average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.7\times$ </tex-math></inline-formula> ) faster than a state-of-the-art CPU does while consuming only 2.5% energy with similar docking accuracies. Compared to the GPU-accelerated implementation or Vina-GPU, the average energy consumption of Vina-FPGA is merely 45%.

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floorplanning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

Low cost imaging sensors and powerful embedded computers have taken the field of computer vision to new heights. One of the challenges that remains is to shorten the development time that it takes to target one’s algorithm to hardware. This work details the steps necessary to use Model Based Design to first simulate and then to target a stereo rectification and undistortion algorithm to an embedded FPGA system on chip hardware target. This work demonstrates what the future of FPGA-based algorithm development might look like by making use of closed loop design techniques with the aid of novel Model Based Design tool flows. Hardware-abstracted constructs such as ’virtual cameras’ and the capability of pulling images off the target system and feeding them back into the simulation model help to minimize discrepancies between simulation and hardware domains, ultimately reducing the total development time. The developed system is a deterministic real time and low latency implementation as it does not rely on external off chip memory as all necessary buffering is done in the internal FPGA block RAM structures. The design is capable of processing 752x480 images at pixel line rates and is easily expandable to high resolution images. The algorithm being developed is not being touted as novel, rather that it is sufficiently complex in order to demonstrate the power of the Model Based Design tool flows.