An Advanced Method of Testing Memories Using a Vedic March Algorithm

Abstract

ABSTRACT Nowadays, as the technology grows the size of the chip decreases, and RAM testing ibecomes more critical whose input and output ports are not controlled directly through the input or output pins of an IC. Because of the absence of controllability of RAM at the input or observing the output ports, testing is a tougher and more challenging effort. Multiple RAM testing is the main theme of the paper. Existing ways of testing RAMs for testing address data in random ways and missed corner cases, in the proposed system we come up with the new idea of testing RAMs using VMA (a Vedic March Algorithm). In the existing system using VMA tested a single RAM and by using a similar technique added multiple blocks of RAM and tested using VMA, for input generation of bits we used a BIST controller. we proved the 60% efficiency of the output is more comparable to the existing designs which standardize to improve march algorithms and observed a 10% decrease in the area compared to the existing systems. The proposed system uses a built-in self-test for generating a randomized cyclic address with the Vedic march algorithm which improves the level of testing of RAMs by randomizing reads and write flows to check and achieve higher efficiency. Simulation results are carried out by Synopsys VCS using Verilog HDL of reads and writes of different memories using March techniques.