Railway Interlocking System Research Articles

Algorithmic Decomposition of Railway Objects for Distributed Interlocking System

Railway interlocking systems can be implemented as distributed systems, where each part of a station is handled by a separate logical unit. The logical units of such systems form a network and communicate by interchanging messages. Such distributed architectures are well known in large industrial control systems. There are several design practices and also algorithmic task partitioning methods that are applicable in distributed control systems. Some of such methods can also be adapted in designing of railway interlocking systems as well. In the case of such systems, the communication time between components must be kept low. Namely each separate controller in a given route must be able to exchange their internal state within a limited time in order to permit the train movement authorization. This limitation could cause high traffic load, if every logical unit would be interconnected with each other. Therefore, the main goal of the minimization is to reduce the number of connections between logical units. This can achieved by distributing and assigning the topological railway objects to certain logical units.

Performance evaluation of electro-mechanical railway interlocking system for digital twin application

The industries engaged healthcare, manufacturing, and construction automated with exquisite creativity and innovation at the doorstep of Industry 4.0. In this process, digital twins are diligently used to supplement industrial processes, reduce costs, monitor assets, streamline maintenance, reduce downtime, and enable the creation of connected goods. The research is aimed at finding the digital representation of electro-mechanical railway interlocking elements are simulated and its functionality is verified accordingly. With respect to carry out this research, the Indian Railways Mangalagiri Railway Station blueprints were collected to represent the physical Model which consists of signals, points, a crank handle, an LC gate, and many more elements. In this paper, three interlocking elements such as points, crank handle, and LC gate, are analysed, modelled, and simulated by using Model Sim ME of Libero SoC software. Representation of these digital elements were developed using a smart design canvas. Therefore, the proposed methodology will enhance the safety measures and security levels of the train movements and reduces the time required to replace the faulty relay. Similarly, in future, the proposed model could be dumped into the FPGA kit to verify the real-time data for finding the faulty relay in the relay-based interlocking system.

A fast and general algebraic approach to Railway Interlocking System across all train stations

<abstract><p>Railway interlocking systems are crucial safety components in rail transportation, designed to prevent train collisions by regulating switch positions and signal indications. These systems delineate potential train movements within a railway station by connecting sections into routes, which are further divided into blocks. To ensure safety, the system prohibits the simultaneous allocation of the same block or intersecting routes to multiple trains. In this study, we characterize the 'interlocking problem' as a safety verification task for a single real-time station configuration, rather than a 'command and control' function. This is a matter of verification, not solution, typically managed by an interlocking system that receives movement authority requests. Over the years, we have developed various algebraic models to address this issue, suggesting the potential use of computer algebra systems in implementing interlocking systems. However, some of these models exhibit limitations. In this paper, we propose a novel algebraic model for decision-making in railway interlocking systems that overcomes the limitations of previous approaches, making it suitable for large railway stations. Our primary objective is to offer a mathematical solution to interlocking problems in linear time, which our approach accomplishes.</p></abstract>

Integral railway interlocking system and its assessment according to European standards

This paper analyses the component of the Integrated Interlocking System which forms the central logical and functional unit implementing all logical and computational functions necessary for railway traffic control in the Railway 4.0 concept. The main principle is that this approach centralizes the technology of station interlocking system, track line interlocking systems, level crossing interlocking systems and the functions of train interlocking system – the line part of ETCS L2/3 radio block control panel (RBC). The operation control is centralised to the controlling dispatcher centres.The paper discusses the concept of integrated interlocking system including safety issues addressed from the perspective of the requirements of CENELEC standards EN 50126, EN 50128 and EN 50129. These requirements are addressed from the perspective of the authors of the paper, who also work as independent assessors of the safety of railway control and command systems.

Compositional Verification of Railway Interlocking Systems

Model checking techniques have often been applied to the verification of railway interlocking systems, responsible for guiding trains safely through a given railway network. However, these techniques fail to scale to the interlocking systems controlling large stations, composed of hundreds and even thousands of controlled entities, due to the state space explosion problem. Indeed, interlocking systems exhibit a certain degree of locality that allows some reasoning only on the mere set of entities that regard the train movements, but safe routing through a complex station layout requires a global reservation policy, which can require global state conditions to be taken into account. In this article, we present a compositional approach aimed at chopping the verification of a large interlocking system into that of smaller fragments, exploiting in each fragment a proper abstraction of the global information on routing state. A proof is given of the thesis that verifying the safety of the smaller fragments is sufficient to verify the safety of the whole network. Experiments using this compositional approach have shown important gains in performance of the verification, as well as in the size of affordable station layouts.

Decision making in railway interlocking systems based on calculating the remainder of dividing a polynomial by a set of polynomials

<abstract><p>Decision-making in a railway station regarding the compatibility of the positions of the switches of the turnouts and the indications (proceed/stop) of the railway colour light signals is a safety-critical issue that is considered very labor-intensive. Different authors have proposed alternative solutions to automate its supervision, which is performed by the so-called railway interlocking systems. The classic railway interlocking systems are route-based and their compatibility is predetermined (usually by human experts): only some chosen routes are simultaneously allowed. Some modern railway interlocking systems are geographical and make decisions on the fly, but are unsuitable if the station is very large and the number of trains is high. In this paper, we present a completely new algebraic model for decision-making in railway interlocking systems, based on other computer algebra techniques, that bypasses the disadvantages of the approaches mentioned above (its performance does not depend on the number of trains in the railway station and can be used in large railway stations). The main goal of this work is to provide a mathematical solution to the interlocking problems. We prove that our approach solves it in linear time. Although our approach is interesting from a theoretical perspective, it has a significant limitation: it can hardly be adopted in an actual interlocking implementation, mainly due to the heavy certification requirements for this kind of safety-critical application. Nevertheless, the results may be useful for simulations that do not require certification credit.</p></abstract>

Impact Assessment of Interlocking Systems on Single-Track Railway Lines as a Measure Leading to Resilient Railway System

Railway systems should be resilient to play a key role in creating sustainable development. Single-track railway lines are seen as potential bottlenecks due to limited capacity. More advanced railway interlocking systems (such as ETCS or satellite-based control systems) are being developed. On the other hand, the installation of these interlocking systems is a complex and time-consuming and costly task. For this reason, it is necessary to recognize the impact of potentially installed system with capacity, stability of timetable, quality, and other associated effects. The assessment is based on a set of simulation experiments using stochastic microscopic simulation model in the OpenTrack software tool. The focus is on railway operation with automatic block and automatic line blocking systems. If these two systems will have positive capacity effects, it is a basic presumption also for systems such as moving block (e.g., ETCS L3) to be effective. Research has shown that the significance of such measures can be best supported by linking to a matching timetable concept that will make full use of the benefits offered by these interlocking systems. The results reached in this research should be potentially applied, for example, by prioritizing of single-track railway lines for possible installation of such interlocking system. It can be achieved based on the capacity and operational effects examined.

I*-Based Goal-Oriented Modeling and Requirements Specification of an Urban Railway Interlocking System

Urban railway interlocking system is a safety-critical system, for which interlocking rules are well-defined by international standards to assure safe operations. However, it is very difficult to extract all of the safety requirements in the requirements engineering stage itself and construct a goal model as well. One approach to fulfill this goal is to extract safety requirements from regulations and analyze them at the early stage of the model. Improper specifications regarding the environs of an interlocking system are realized to be accountable for any faults in requirements specifications. Furthermore, nonfunctional requirements are kept aside from requirements specifications. To make an interlocking system operate in an ultra-dependable range we need to address variability issues, so in this paper, we used i*-based goal-oriented requirements language called TGRL to address variability issues as well as blend early and late requirements. The developed model can also be visualized and analyzed using jUCMNav. Finally, the safety requirements to be verified are specified with Formal Tropos, a formal specification language for the i* model.

A Survey on Formal Specification and Verification of Smart Mass Transit Railway Interlocking System

Nowadays interest in Smart Mass Transit Rail has grown-up to a large extent in a metropolitan area as the need for urban mobility has increased steadily. The reliability of software being used in such mass transit rail is crucial for us, specifically when software crashes may lead to catastrophic loss of human life and assets. For example, when we travel by metro it is essential for us that the interlocking system software controlling the metros are accurate so collisions and derailment are prevented. The reliability and safety of such interlocking systems are made on the precise functional requirements specification and verification respectively. Therefore, the precise functional requirements specification and verification of such interlocking systems represent a challenge in an active research area, so in this paper, we survey various articles in this field and discuss their consequences.

From French National Signaling Systems to ERTMS: Considering the Evolution of Track-Side Systems

In France, the railway lines are divided into the national and international lines. While the former has a proper implementation of the railway signalling systems as relay-based or computer-based systems, the latter follows the guidelines defined by the ERTMS standards, focusing on the interoperability throughout Europe. In a previous work we presented how the national legacy relay-based Railway Interlocking Systems (RIS) can evolve to use a computer-based technology in order to benefit from its advantages. In this present article, we present how these computer-based systems can be used in order to allow the evolution from a national line towards an ERTMS compliant international line. This proposition is based on the fact that the previous work provides the support for evolving the track-side technologies with, for instance, the use of GNSS for the train geo-localisation instead of electrical circuits-based train detection systems. Then, a discussion of the impact of this evolution over the system safety is presented.

Automatic generation of VHDL code for a railway interlocking system

This article introduces a novel technique to automatically analyse a railway network geographical representation and produce a suitable FPGA railway interlocking system by generating its VHDL hardware description. This approach accelerates the design, implementation and testing phases on different topologies. We review the automated tools developed - which are part of a comprehensive workflow - and present the results for topologies of varying complexities.

Automatic generation of VHDL code for a railway interlocking system

Automatic generation of VHDL code for a railway interlocking system

Towards safe and secure computer based railway interlocking systems

Towards safe and secure computer based railway interlocking systems

Stepwise development and model checking of adistributed interlocking system using RAISE

Abstract This paper considers the challenge of designing and verifying control protocols for geographically distributed railway interlocking systems. It describes how this challenge can be tackled by stepwise development and model checking of state transition system models in a new extension of the RAISE Specification Language. Railway interlocking systems are reconfigurable systems which can be configured by supplying data describing the network to be controlled and other details. Therefore, such systems are natural candidates for being modelled by generic state transition systems, which abstract away from the concrete configuration at the time of modelling, and can later be instantiated with concrete data. For a real-world case study, a generic state transition system is developed in steps, starting with an abstract model of the essential system behaviour and incrementally adding details and restrictions. The stepwise development method allows different variants of the control protocol to be explored. The generic models are instantiated with concrete configuration data, after which desired properties, in particular safety properties, of the system models are verified using model checking.

FPGA implementation of a critical railway interlocking system

FPGA implementation of a critical railway interlocking system

Construction of formal models and verifying property specifications through an example of railway interlocking systems

Abstract The use of formal modeling has seen an increasing interest in the development of safety-critical, embedded microcomputer-controlled railway interlocking systems, due to its ability to spec...

An Algebraic Approach to DC Railway Electrification Verification

Grobner bases have been applied to a number of problems related to the verification of Knowledge-Based Systems (KBS) and other problems within graph theory. In particular, the authors have developed in previous papers algebraic approaches to decide whether a situation in a railway interlocking system is safe or not. These algebraic approaches stand out because of the briefness of the code (as they use implementations of well-known algorithms for solving linear or algebraic systems provided by computer algebra systems). The authors have also developed a matrix-based computer tool that helps an expert to check whether a proposed railway electrification scenario (given through the topology of the railway station and the position of the isolation devices and the position and state of the “electrical bypasses” and feeders) fulfills the mandatory requirements of the Spanish railway infrastructure administrator (ADIF) for 3000 V railway electrifications or not. The second author works in the field of railway electrifications and he compares the present-day methods for verification of railway electrifications with the way KBS were verified in the past (manually by experts). In this article we approach this latter problem using algebraic techniques. The new computer tool is based on an algebraic translation of the problem (instead of based on the use of matrices) and is really simple and fast. Determining which electrification sections are under electric tension is computed solving linear systems (because in this case the graph is undirected and no polynomials of degree $$>\,1$$ arise in the algebraic translation, so it is not necessary to use Grobner bases, unlike in the two problems mentioned in the beginning of the Abstract). Therefore far bigger railway facilities can be addressed than if non-linear systems were involved.

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.

FPGA implementation of a critical railway interlocking system

An interlocking is a railway system that automatically controls that changes in routes are safely managed, avoidingtrain crashes and derailments. This article presents an analysis of the state of the art technology used in several commercial interlocking equipment. Based on this analysis, design and implementation of an interlocking system architecture in FPGA technology is proposed. Appropriate techniques are applied to achieve the required level of security. The scalability of the design is also analyzed and conclusions are presented.

Safety Verification of a Train Interlocking Timed Automaton Model

This paper presents an application of formal methods based on model checking techniques for safety verification of a railway interlocking system. The proposed model checking techniques are implemented on a timed automaton model of the considered interlocking systems and with respect to safety operational specification that are expressed as computation tree logic formulas. The freely available UPPAAL model checker is used to perform the model checking task and simulation results of the performed verification are presented.