Rail Voltage Research Articles

Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology

We present a dynamic body charge modulation technique to improve the matching of CMOS device threshold voltage (V/sub t/) characteristics in the partially depleted silicon-on-insulator (SOI) technology. For a latch-type sense amplifier in the SRAM complementary bitline structure, a pair of-charging FETs are employed to bring the bodies of cross-coupled sensing devices to the voltage rail. In doing so, operating history-dependent body potential mismatches are eliminated for every access cycle. Body-contacted FETs are returned to their floating body states when the charging action is completed. This technique achieves repeatable low-V/sub t/ and high-performance operation simultaneously. The pulse signal controlling body charging is not constrained by a stringent timing requirement. Therefore, its effectiveness is insensitive to the body contact quality of sensing FETs. This technique demonstrates a significant leverage for high-performance RAM circuits. It also offers the advantages of speed and noise immunity in the low-voltage low-power operating regime.

Shunt-excited doubly salient 8/6-switched reluctance machine

The performance of a doubly salient 8/6-switched reluctance motor using a shifted fully pitched winding configuration is investigated. The self and mutual inductance characteristics of the machine windings are fundamental to torque generation and are therefore evaluated both theoretically and experimentally. Finite element analysis has been used to investigate theoretical motor-torque capability. Simulation and experimental results for different commutation schemes and their corresponding torque waveforms are investigated for low levels of torque and at low speed. Experimental results are presented for the operation of the machine up to full-load torque. A simple DC rail voltage boosting circuit is shown to enhance the current-control capabilities of an IGBT-based converter. The possibility of driving the machine using a two-switch power converter is also discussed.

Low Voltage Rail to Rail CMOS Current Feedback Operational Amplifier and its Applications for Analog VLSI

This paper presents a new CMOS current feedback operational amplifier (CFOA) with rail to rail swing capability at all terminals. The circuit operates as a class AB for lower power consumption. Besides operating at low supply voltages of ±1.5 V, the proposed CFOA has a standby current of 200 μA. The proposed CFOA circuit is thus a versatile building block for low voltage low power applications. The applications of the CFOA to realize a transconductor/multiplier cell, MOS-C differential integrator, MOS-C bandpass filter and MOS-C oscillator are given. PSpice simulations based on 1.2 μm level three parameters obtained from MOSIS are given.

Secondary arc dynamics in a railgun bore

We have conducted a series of experiments on the growth of secondary arcs in railgun bores. The experimental results indicate that the secondary arc grows bigger as the stored energy of the capacitor bank becomes higher and as the diameter of the railgun bore decreases. The growth of the secondary arc led to the disappearance of the plasma armature in the worst case, which was performed with a small caliber railgun driven by a high stored energy in the capacitor bank. It was found that the spatial distribution of the rail voltage along the bore arc is closely related to the growth of the secondary arcs. The rail voltage at a given point in the railgun bore starts to rise when the plasma armature arrives and after passage it decreased gradually. The region of maximum rail voltage moves with time and propagates from the breech to the muzzle. While the secondary arc, which was far behind the plasma armature, travelled to the muzzle, its motion was considerably influenced by the spatial distribution of the rail voltage. The secondary arc grew only when it moved with the propagation of the maximum rail voltage. When the secondary arc was left behind from the propagation of the maximum rail voltage, it faded gradually or stopped growing.

Low-voltage low-power CMOS current conveyors

New CMOS rail to rail second generation current conveyor circuits are proposed. First a class A current conveyor circuit which operates from a single supply of 1.5 V with a rail to rail voltage swing capability is given. The circuit is then modified to work as a class AB while maintaining the rail to rail swing capability. The class AB circuit works from supply voltages down to +1.1 V with standby current of 56 /spl mu/A. These new current conveyor realizations are insensitive to the threshold voltage variation caused by the body effect, which minimizes the layout area and makes both circuits a valuable addition to the analog VLSI libraries. PSpice simulation confirms the attractive properties of the proposed circuits.

Applications to digital logic of YBCO dc SQUIDs

The advent of High-Tc materials has generated excitement for developing faster and more reliable superconducting computer systems. The new materials allow for the use of relatively inexpensive cryo-coolers, allowing portability and furthering interest in space-based on-board processing. Presently available YBCO junctions are, however, naturally damped SNS devices which do not have the hysteresis that most traditional superconducting circuits rely upon. A simple alternative to these architecture is the SAIL architecture we have developed at TRW 1). These are composed of a Series Array of dc SQUIDs (Interferometer Logic), and use non-hysteretic devices. It is much like CMOS semiconductor designs, including the voltage bias, in contrast to current bias more typical of superconducting circuits. Further, it relies on only a few SQUIDs to implement all of the binary logic functions, including a very natural invertor, without recourse to dual-rail outputs. Since the logical function of a gate is determined by the final wiring layer, gate array applications are a natural use of this architecture. In 1991 we published a demonstration of low speed operation using then available YBa 2 Cu 3 O 7 dc SQUIDs 2). These tests showed mat the devices will work using supplied voltage rails and do not latch at intermediate voltages as early models had predicted. Our current efforts are geared toward placing much improved devices 3),4) in this architecture and testing at high (2 GHz and higher) speed at higher temperatures (above 65 K) Our modelling indicates that generally speed will be limited by the inductive input coils, a problem not faced by RSFQ 5) Iogic fçr example. The larger SAIL operating margins, it's simplicity of design, and more generous production latitude will allow early use in many important application. SAIL modelling and experimental results will be compared to other designs, and RSFQ in particular, with respect to speed, performance, and margins.

On-line simulation of voltage regulation in autotransformer-fed AC electric railroad traction networks

Simulation algorithms to model the voltage distribution characteristics in AC autotransformer-fed railroads with single- and double-end supply are described. The theory is based on the solution of algebraic equations for a single train, moving along a track section represented as a coupled transmission line. The simulation was implemented on a PC with continuous displays of the catenary and rail voltages, and an historical record of the train voltage for movement at constant speed along the section. The simulator enables rapid parametric analyses to be made in order to optimize the power feeding arrangement, and sample displays of catenary, rail, and train voltages are given for single train operation under constant current and constant power.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In situ determination of rail track electrical impedance and admittance matrix elements

A novel differential excitation technique is described for the experimental determination of the elements of rail track impedance and admittance matrices from measurements of rail voltages, and currents on a short, isolated track section. The establishment of a common earth point along the track is unnecessary, although rail breaks and driven earth rods at the feed and remote ends of the test section are required. Rail self and mutual impedance and admittance measurements are reported for a single railway track, for a frequency of 50 Hz. >

Experimental measurement of railgun performance

A railgun has been developed to investigate the mechanisms which prevent projectiles from reaching hypervelocity. The railgun is 950 mm long and has a 10 mm square bore. The insulators are transparent polycarbonate, which permits observation with a streak camera. The power supply is a 6-mF, six-stage pulse-forming network, which can control the waveform of the current by varying the inductances. The rail current and voltage were measured. Power distribution in the railgun can be calculated from the results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Spatial characteristics of the EML plasma armature and the dependence on plasma composition

A simplified picture of a radiation-dominated plasma armature of an electromagnetic launcher (EML) is developed to evaluate in quasi-steady-state its spatial characteristics and their dependence on plasma composition, applied electric and magnetic fields, and possible temporal changes. A graphical solution of the energy balance equation is found which permits quick visualization of the effects of changing rail voltage or bore diameter. It is found that metallic vapor armatures will have plasmas extending to the highest expected pressures near the projectile. However, armatures consisting of the ablation products of G-9 or Lexan insulators or other nonmetallic plasmas such as hydrogen or argon cannot satisfy the energy balance conditions at high pressures unless the electric field is sufficiently high. Such armatures may not develop the desired magnetic pressure gradient in their leading edge to accelerate the projectile, with possible performance degradation. At low pressures (1-10 atm) in the trailing edge of the armature, the electrical conductivity can be significantly reduced by the high transverse magnetic field. It is concluded that this extended tail of low temperature plasma could be of importance in restrike phenomena.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-voltage rail-supply-insensitive PTAT current generator

The interconnection of a previously described voltage-following current mirror and a 'Widlar'-type current sink realises a PTAT current generator that exhibits a low sensitivity to rail-supply variations, even at rail voltages less than 2 V.

A comparative study of CMOS processes for VLSI applications

A comparative study of simulated circuit performance has been made in order to determine the optimum process parameters for p-well CMOS with feature sizes of between 1 and 2 µm. it has been found that for the process considered, best speed, Power, and packing density are achieved with a substrate concentration of between 3 × 1015and 1016cm-3and an operating voltage which is as low as possible. Higher speed can be attained at the expense of considerably more power dissipation through the use of a higher rail voltage. Silicon-on-insulator CMOS has been considered as an alternative to p-well CMOS. This technology can be expected to out-perform small geometry bulk silicon CMOS if recent improvements in material quality can be maintained.

A new monostable circuit with zero stand-by power

The novel interconnexion of a bridge timing circuit, a switched comparator, and a complementary transistor latching scheme, permits the design of a monostable circuit which consumes `zero? standby power and has a pulse width T = CR±3% (C and R being externally connected timing components) for a rail voltage in the range 3V to 30V.

Simulation Of Rail Voltage And Earth CurrentIn A PC-based Traction Power Simulator

Electrical circuit simulation by setting up nodal voltage equations and inverting a conductance matrix is a powerful CAE tool. Running large models on PCs, however, requires economic computing and storage requirements. This paper describes an algorithm for compacting intermediate storage necessary for solving circuit models with a large, sparse conductance matrix. The algorithm is based on targeted directed elimination followed by Gaussian elimination with back substitution. An example is given of an electrical calculation in a timestepping railway traction simulator. The circuit represents a double-track light rail system with one branch. Outputs are given for train voltage, substation busbar feeding conditions and rail voltage, the latter also giving information about earth current.