Radiation-hardened Design Research Articles

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event–multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.

A 4-Channel 12-Bit High-Voltage Radiation-Hardened Digital-to-Analog Converter for Low Orbit Satellite Applications

This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5- $\mu \text{m}$ Bi-CMOS technology to achieve the functionality across a wide-temperature range from −55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of −0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from −55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm $\times7$ mm in total including pads (core active area of 4 mm $\times5$ mm excluding pads) and consumes less than 525 mW, output voltage ranges from −10 to +10 V.

Radiation-Hardening Techniques for Spin Orbit Torque-MRAM Peripheral Circuitry

Magnetic random access memory (MRAM) is experimentally proved intrinsically immune to radiation effects including heavy-ion irradiation and total ion dose as the data are represented by the spin instead of charges. Hence, it is considered as a promising candidate for aerospace and avionic electronics. However, its CMOS peripheral read/write circuits are much more vulnerable to radiation-induced single-event upset (SEU) and double-node upset (DNU) induced by charge sharing. This paper presents a novel radiation-hardening design of the peripheral circuitry for spin orbit torque (SOT)-MRAM to address abovementioned issues effectively. Transient simulations are performed based on a physics-based SOT-magnetic tunnel junction compact model and a 65 nm CMOS design kit. Simulation results validate that the proposed hardening read/write circuits are strongly robust against SEUs and DNUs. Furthermore, the proposed hardening read circuit shows the improvement of hardware area and reliability compared with the previous works.

Radiation-hardening and testing approach for bringing a terrestrial RF transceiver to the space environment

Present-day space-qualified component performance and flexibility is limited when compared to the capabilities of electronic parts for terrestrial applications. While some component manufacturers provide ranges of products that are radiation-hardened and radiation-tolerant, their computational performances are sometimes limited. In other cases, it is even impossible to find high reliability parts that match the required functionality, such as, for instance, radio-frequency components for a highly-dynamic software-defined radio platform. In fact, when talking about communications, terrestrial technologies are far more advanced than those applied in space. Motivated by the global mobile communications market, permanently seeking new products and development areas, these technologies experience an unparalleled evolution. Then, how can Space benefit from these technological advances on Ground, without sacrificing reliability?Such challenge was faced in the development of an Inter-Satellite Link (ISL) for the ESA Proba-3 formation flying mission. The baseline technology was based on a terrestrial software-defined transceiver architecture, relying on state-of-the-art electronic parts. For this reason, and to avoid a major redesign of the ISL data link, the approach selected to handle radiation in the ISL units was threefold: (i) Develop a mechanical design that is able to provide considerable shielding to the electronic components inside, through an increase of thickness. The additional mass is compensated by the miniaturisation levels attained by not using bigger and heavier radiation-hardened components; (ii) Implement design techniques that help to mitigate the single-event effects caused by high-energised particles. Techniques include latch-up protection, voting systems on the processors or Triple Modular Redundancy (TMR); and (iii) Perform radiation testing on selected critical components or assemblies, against the Proba-3 radiation environment, and devise backup component replacement strategies.This paper describes the approach being followed for the radiation qualification of the Proba-3 ISL unit, based mostly on commercial parts, and the different challenges faced throughout the process. It covers the three levels described before: mechanical shielding, radiation-hardening design techniques and radiation verification testing, including analysis and test results. Additionally, the paper addresses the benefits and technical and economical viability of this integrated strategy to increase the variety of the space-approved parts, in order to enable better-performing satellite missions and bridge the existing gap between space and terrestrial technology.

Проблемы информационно-коммуникационного взаимодействия при проектировании радиационно- стойких изделий от элементной базы до конечных устройств на примере использования отечественной САПР

Проблемы информационно-коммуникационного взаимодействия при проектировании радиационно- стойких изделий от элементной базы до конечных устройств на примере использования отечественной САПР

Dependence on Base Width and Doping Concentration of Current Degradation in Gate-controlled Lateral PNP Bipolar Transistors Exposed to Reactor Neutrons and Gamma Rays

Bipolar devices are widely used in the nuclear reactor control system, and the radiation effects on them are very important to reactor operation. The lateral PNP bipolar transistor is a radiation-sensitive structure in bipolar integrated devices. Its degradation under irradiation is the primary cause for functional failures of bipolar integrated devices. It is useful to understand the radiation response of the transistors to find better design strategies for radiation hardness. Three kinds of gate-controlled lateral PNP bipolar transistors (GCLPNPs) with different base widths and doping concentrations are specially designed to explore base current degradation induced by reactor neutrons and gamma rays. Dependence on base width and doping concentration of the degradation is analyzed in this work and the results are beneficial to radiation-hardening design of the lateral PNP bipolar transistor.

Development of single-event-effects analysis system at the IMP microbeam facility

Single-event-effects (SEEs) in integrated circuits (ICs) caused by galactic single ions are the major cause of anomalies for a spacecraft. The main strategies to decrease radiation failures for spacecraft are using SEEs less-sensitive devices and design radiation hardened ICs. High energy ion microbeam is one of the powerful tools to obtain spatial information of SEEs in ICs and to guide the radiation hardening design. The microbeam facility in the Institute of Modern Physics (IMP), Chinese Academy of Science (CAS) can meet both the liner energy transfer (LET) and ion range requirements for SEEs simulation experiments on ground. In order to study SEEs characteristics of ICs at this microbeam platform, a SEEs analysis system was developed. This system can target and irradiate ICs with single ions in micrometer-scale accuracy, meanwhile it acquires multi-channel SEE signals and maps the SEE sensitive regions online. A 4-Mbit NOR Flash memory was tested with this system using 2.2GeVKr ions, the radiation sensitive peripheral circuit regions for SEEs of 1 to 0 and 0 to 1 upset, multi-bit-upset and single event latchup have been obtained.

A 12-bit, 1 MS/s SAR-ADC for a CZT-based multi-channel gamma-ray imager using a new digital calibration method

The successive approximation register-analog to digital converter (SAR-ADC) is widely used in the CdZnTe-based gamma-ray imager because of its outstanding characteristics of low power consumption, relatively high resolution, and small die size. This study proposes a digital bit-by-bit calibration method using an input ramp signal to further improve the conversion precision and power consumption of an SAR-ADC. The proposed method is based on the sub-radix-2 redundant architecture and the perturbation technique. The proposed calibration algorithm is simpler, more stable, and faster than traditional approaches. The prototype chip of the 12-bit, 1 MS/s radiation-hardened SAR-ADC has been designed and fabricated using the TSMC 0.35 μm 2P4M CMOS process. This SAR-ADC consumes 3 mW power and occupies a core area of 856× 802μm2. The digital bit-by-bit calibration algorithm is implemented via MATLAB for testing flexibility. The effective number of bits for this digitally calibrated SAR-ADC reaches 11.77 bits. The converter exhibits high conversion precision, low power consumption, and radiation-hardened design. Therefore, this SAR-ADC is suitable for multi-channel gamma-ray imager applications.

电荷耦合器件中子辐照诱发的位移效应

Displacement damage effects due to neutron irradiations of charge coupled devices were presented through the analysis of the dark signals behavior in pixel arrays. When the fluence of neutron reached the predetermined point,the change of dark signal,dark signal non-uniformity,charge transfer efficiency and saturated output signal was measured off line. The major effect of neutron induced displacement damage on charge coupled device is the increase in dark signals as a result of carrier generation in the bulk depletion region of the pixel. Although the increase in the mean dark signals with neutron irradiation is important,the dark signals non-uniformity is generally the biggest concern for charge coupled device applications in space. Very large dark signals pixels can be produced when a collision occurs in a high electric field region of a pixel as a result of electric field enhanced emission. Another important performance parameter for a charge coupled device is the charge transfer efficiency,which is the fraction of signal charge transferred from pixel to pixel during read out. If a signal charge is trapped by neutron induced defect,and remains trapped for more than one clock cycle,it will be lost from the signalcharge packet. Saturation output signal voltage does not have any obvious degradation even at the highest DDD level. The research will help the designers to know the radiation damage in charge coupled device and improve the tolerance by radiation hardening design.

A reference voltage in capacitor–resister hybrid SAR ADC for front-end readout system of CZT detector**Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (No. 61376034), and the Shaanxi Province Science and Technology Innovation Project (No. 2015KTZDGY03-03).

An on-chip reference voltage has been designed in capacitor–resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μm 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80 °C, the temperature coefficient is 12.2 ppm/°C. The PSRR was −70 dB @ 100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449 × 614 μm2. The total power consumption is only 1.092 mW.

An introduction to CPU and DSP design in China

In recent years, China has witnessed considerable achievements in the production of domesticallydesigned CPUs and DSPs. Owing to fifteen years of hard work that began in 2001, significant progress has been made in Chinese domestic CPUs and DSPs, primarily represented by Loongson and ShenWei processors. Furthermore parts of the CPU design techniques are comparable to the world’s most advanced designs. A special issue published in Scientia Sinica Informationis in April 2015, is dedicated to exhibiting the technical advancements in Chinese domestically-designed CPUs and DSPs. The content in this issue describes the design and optimization of high performance processors and the key technologies in processor development; these include high-performance micro-architecture design, many-core and multi-core design, radiation hardening design, highperformance physical design, complex chip verification, and binary translation technology. We hope that the articles we collected will promote understanding of CPU/DSP progress in China. Moreover, we believe that the future of Chinese domestic CPU/DSP processors is quite promising.

The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS

A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320Mbit/s and generates retimed data as well as 40, 80, 160 and 320MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable phase with a resolution of 195ps. An internal calibration mechanism enables the eCDR to lock on incoming data even without the availability of any form of reference clock. The radiation-hard design, integrated in a 130nm CMOS technology, operates at a supply voltage between 1.2V and 1.5V. The power consumption is between 28.5mW and 34.5mW, depending on the settings. The eCDR can achieve a very low RMS jitter below 10ps.

The supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal—oxide—semiconductor static random-access memory cells

Using computer-aided design three-dimensional simulation technology, the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated. It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing, which is quite attractive for dynamic voltage scaling and subthreshold circuit radiation-hardened design. Additionally, the effect of supply voltage on charge collection is also investigated. It is concluded that the supply voltage mainly affects the bipolar gain of the parasitical bipolar junction transistor (BJT) and the existence of the source plays an important role in supply voltage variation.

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160MHz output and 22.5° for the 320MHz output. The radiation-hard design, integrated in a 130nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Radiation Effects in MOS-based Devices and Circuits: A Review

Radiation effects in microelectronic components have been studied for several decades for military and space applications. Understanding radiation effects in electronics is a complex and continually evolving challenge. In this paper, we present an extensive literature review pertaining to the state-of-the-art issues in radiation effects and radiation-hardened circuit design. Various research papers, books and application notes were referred, which take care of various aspects of understanding of radiation effects. In particular, this review gives a bibliographical survey of the current research efforts in the area of radiation effects in metal-oxide-semiconductor based devices and circuits. The paper also presents some of the challenges anticipated in the years to come and enlists further scope for research. A full description of the various methods is beyond the scope of this article; instead, the focus is on providing primary developments that have taken place in the area of radiation effects.

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Since single event transient pulse quenching can reduce the SET (single event transient) pulsewidths effectively, the charge collected by passive device should be maximized in order to minimize the propagated SET. From the perspective of the layout and circuit design, the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay, which sheds new light on the radiation-hardened ICs (integrated circuits) design. Studies show that the SET pulsewidths of propagation are not in direct proportion to the LET (linear energy transfer) of incident particles, thus the defining of the LET threshold should be noted when SET/SEU (single event upset) occurs for the radiation-hardened design. The capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is low. Therefore, radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit.

Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si–SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

Design and Assessment of a Circuit and Layout Level Radiation Hardened CMOS VCSEL Driver

The radiation hard design of a 155 Mb/s, 0.7 mum CMOS driver for a vertical-cavity surface-emitting laser (VCSEL) is presented. The circuit features enhanced tolerance to radiation induced shifts in the device characteristics by employing a replica-based feedback mechanism. The layout was achieved using an in-house developed radiation hardened component library. At a low dose rate of 4.5 Gy/h or 450 rad/h, the output current remains constant up to at least 3.5 kGy. At a dose rate of 21 kGy/h, the output current of the driver drops by 10% at a dose of 3.5 MGy and breaks down completely at 5.5 MGy.

Progress in the ALICE silicon pixel detector

The ALICE silicon pixel detector comprises two barrel layers with ≈10 7 hybrid pixel cells. The basic detector element is a half-stave, an array of two ladders, each consisting of 5 pixel chips bump bonded to a Si sensor matrix. The ladders are mounted on a low-mass aluminium/polyimide multilayer bus for power distribution and signal routing. Each half-stave is controlled and read out via a multi-chip-module. All chips are ASICs in CMOS 0.25 μm technology with radiation hard design. Data transfer is done on optical fibres. The system and recent progress in its implementation are overviewed.