Quaternary Multiplexer Research Articles

A novel low complexity and energy-efficient method to implement quaternary logic function in nanoelectronics

One of the main problems in chip design is the huge number of interconnections between digital blocks. Using Multi-valued logic can lead to the reduction of interconnections. So, the chip area and power dissipation in connections could be reduced. To fulfil the multi-valued logic aim, however, the number of transistors should be reduced considerably. In this paper, first, a novel quaternary multiplexer is designed. Then, a novel method for implementing the quaternary logic with single supply voltage is proposed. In this method, first, two binary functions are defined. One of them is activated when the quaternary function is ‘1′ or ‘2’. Another one is activated when the quaternary function is ‘2′ or ‘3’. These binary functions are implemented using the proposed multiplexer. Then, an encoder will create the quaternary function from these binary functions. The number of transistors for the quaternary full-adder designs is reduced from 195 in the previous works to 68 in the proposed method. Also, as the logics ‘1′ and ‘2′ are only produced in the last stage encoder, power consumption and PDP are considerably improved. The simulation results using HSPICE and 32 ​nm Stanford library confirm the correct operation and the considerable PDP improvement from 39.45% to 99.53%, as compared to the previous works.

A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics

Using multi-valued logic (MVL) can reduce the chip area and connections which have direct effect on power consumption. Recently, according to the high ability of nanotechnology in designing MVL, some researchers have focused on this advanced approach. In this paper, primarily, a new design of quaternary multiplexer 4:1 with carbon nanotube field-effect transistors (CNFETs) is proposed. Afterward, quaternary successor, quaternary predecessor, and quaternary second level successor (quaternary second level predecessor) cells are, for the first time, introduced based on CNTFETs. All of the above-mentioned designs are applied to quaternary half adder and quaternary full adder circuits. To approve the designs, the performance is simulated by HSPICE simulator for 32-nm technology with the Stanford compact SPICE model for CNFETs. The results of simulation represent the improved PDP by 67.14% compared to the best current techniques in the literature. All of the proposed designs are evaluated under various operation conditions such as drive ability, fabrication tolerance, and different supply voltages, confirming the performance of proposed circuits.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Power Optimization of Combinational Quaternary Logic Circuits

Due to the need of interconnections design of binary circuits is limited. Interconnection increases area, delay and energy consumption in CMOS digital circuits. A possible solution could be here as, in the same chip area we use more sets of signals. Multiple value logic can decrease average power required for level transitions and reduces the number of necessary interconnections. In this paper we design various combinational modules using Quaternary logic. Various combinational circuits are Quaternary full adder using unique encoding, quaternary encoder & decoder and quaternary multiplexer. These designs are aimed to reduce the transistors used in the implementation of circuits and reducing the power dissipation. Power optimization is achieved using MTCMOS technique. Simulation has been done in Tanner 13 EDA tool on BSIM3 180nm CMOS technology. KeywordsMulti value logic, power optimization, quaternary full adder, quaternary encoder & decoder, quaternary multiplexer and MTCMOS technique. __________________________________________________*****_________________________________________________

All-optical quaternary circuits using quaternary T-gate

In multi-valued logic (radix>2), quaternary multiplexer (also known as T-gate) places a significant role for data transmission and signal processing. Four valued multiplexer transmit one data (from 4-input) to the output corresponding to the one selected input. Any four-valued logic can be implemented using T-gate. So it is called ‘universal’ element. In this paper some all-optical quaternary logical operations, quaternary half-adder, quaternary multiplier and quaternary comparator is proposed and described using only all-optical quaternary T-gate.

High-radix microfluidic multiplexer with pressure valves of different thresholds

We propose high-radix microfluidic multiplexers that effectively address a large number of flow channels with a few control lines having pressure valves of different thresholds. Previous binary multiplexers address only two flow channels by controlling identical threshold pressure valves in two control lines; that is, they address 2(n/2) flow channels by using n control lines. However, the proposed ternary or quaternary multiplexer (high-radix multiplexers) addresses three or four flow channels by controlling two or three kinds of pressure valves in two control lines, respectively. Thus, these multiplexers address 3(n/2) and 4(n/2) flow channels, which are results of increasing the radix from binary to quaternary. In experiments, we designed ternary (two kinds of valves) and quaternary (three kinds of valves) multiplexers and applied them to 3 x 3 and 4 x 4 well arrays with four control lines, respectively. We determine the static/dynamic operating conditions of the pressure valves having different thresholds in the ternary and quaternary multiplexers. Under these conditions, the ternary and quaternary multiplexers successfully address 3 x 3 and 4 x 4 well arrays by controlling two and three pressure valves of different thresholds in four control lines, respectively.

Polarization-encoded all-optical quaternary multiplexer and demultiplexer – A proposal

Multi-valued logic is positioned as a coming generation technology that can execute arithmetic functions faster and with less interconnect than binary logic. Furthermore, nonbinary data storage would require less physical space than binary data. The application of multi-valued digital signals can provide considerable relief of capacity constraints. In electronics many proposals have already been reported. But, here for the first time we propose an all-optical circuit for designing quaternary (four-valued) multiplexer and demultiplexer with the help of some polarization-encoded basic quaternary logic gates (quaternary min and quaternary delta literal). Nonlinear interferometer-based optical switch can take an important role here. The principles and possibilities of design of all-optical quaternary multi-valued multiplexer and demultiplexer circuits are proposed and described.

Quaternary adder, subtractor and multiplier using quaternary multiplexer

Multiplexers, as in the case of binary, are very useful building blocks in the development of quaternary systems. The use of quaternary multiplexer (QMUX) in the implementation of quaternary adder, subtractor and multiplier is described in this paper. Quaternary coded decimal (QCD) adder/subtractor and quaternary excess-3 adder/subtractor realization using QMUX are also proposed

Quaternary adder, subtractor and multiplier using quaternary multiplexer

Quaternary adder, subtractor and multiplier using quaternary multiplexer

Quaternary unary operators

Unary operators are functions of a single variable. Realization of quaternary unary operators (QUOs) using quaternary multiplexer (QMUX) is presented in this paper. QUOs are divided into eight groups on the basis of the number of change overs in the output for an input sequence of 0, 1, 2, 3. This grouping reduces the hardware required to realize them. QMUX with two, three, and four input lines are proposed for the realization of QUOs belonging to the eight groups. A systematic procedure for the selection of QMUX and the implementation of the QUOs are given. The QMUXs are designed using CMOS ICs. The hardware required for their implementation is also discussed.

Design and implementation of quaternary NMOS integrated circuits for pipelined image processing

A pattern-matching procedure for performing four-valued image processing based on cellular logic operation is proposed, allowing two different templates to be processed simultaneously in a pipelined manner. Based on these double pattern-matching cells, a compact NMOS image-processing chip has been implemented. It is demonstrated that the compactness comes from reduced interconnections in the double pattern-matching cells using a quaternary multiplexer or T gates, realized with pass transistors and multiple ion implants.